pci.c 8.6 KB

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  1. /*
  2. * linux/arch/arm/mach-versatile/pci.c
  3. *
  4. * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
  5. * You can redistribute and/or modify this software under the terms of version 2
  6. * of the GNU General Public License as published by the Free Software Foundation.
  7. * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
  8. * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  9. * General Public License for more details.
  10. * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
  11. *
  12. * ARM Versatile PCI driver.
  13. *
  14. * 14/04/2005 Initial version, colin.king@philips.com
  15. *
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/pci.h>
  19. #include <linux/ptrace.h>
  20. #include <linux/slab.h>
  21. #include <linux/ioport.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/init.h>
  25. #include <asm/hardware.h>
  26. #include <asm/io.h>
  27. #include <asm/irq.h>
  28. #include <asm/system.h>
  29. #include <asm/mach/pci.h>
  30. /*
  31. * these spaces are mapped using the following base registers:
  32. *
  33. * Usage Local Bus Memory Base/Map registers used
  34. *
  35. * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
  36. * Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
  37. * IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
  38. * Cfg 42000000 - 42FFFFFF PCI config
  39. *
  40. */
  41. #define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
  42. #define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL)
  43. #define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
  44. #define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
  45. #define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
  46. #define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
  47. #define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
  48. #define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
  49. #define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
  50. #define DEVICE_ID_OFFSET 0x00
  51. #define CSR_OFFSET 0x04
  52. #define CLASS_ID_OFFSET 0x08
  53. #define VP_PCI_DEVICE_ID 0x030010ee
  54. #define VP_PCI_CLASS_ID 0x0b400000
  55. static unsigned long pci_slot_ignore = 0;
  56. static int __init versatile_pci_slot_ignore(char *str)
  57. {
  58. int retval;
  59. int slot;
  60. while ((retval = get_option(&str,&slot))) {
  61. if ((slot < 0) || (slot > 31)) {
  62. printk("Illegal slot value: %d\n",slot);
  63. } else {
  64. pci_slot_ignore |= (1 << slot);
  65. }
  66. }
  67. return 1;
  68. }
  69. __setup("pci_slot_ignore=", versatile_pci_slot_ignore);
  70. static void __iomem *__pci_addr(struct pci_bus *bus,
  71. unsigned int devfn, int offset)
  72. {
  73. unsigned int busnr = bus->number;
  74. /*
  75. * Trap out illegal values
  76. */
  77. if (offset > 255)
  78. BUG();
  79. if (busnr > 255)
  80. BUG();
  81. if (devfn > 255)
  82. BUG();
  83. return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) |
  84. (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
  85. }
  86. static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  87. int size, u32 *val)
  88. {
  89. void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
  90. u32 v;
  91. int slot = PCI_SLOT(devfn);
  92. if (pci_slot_ignore & (1 << slot)) {
  93. /* Ignore this slot */
  94. switch (size) {
  95. case 1:
  96. v = 0xff;
  97. break;
  98. case 2:
  99. v = 0xffff;
  100. break;
  101. default:
  102. v = 0xffffffff;
  103. }
  104. } else {
  105. switch (size) {
  106. case 1:
  107. v = __raw_readb(addr);
  108. break;
  109. case 2:
  110. v = __raw_readl(addr);
  111. if (where & 2) v >>= 16;
  112. v &= 0xffff;
  113. break;
  114. default:
  115. v = __raw_readl(addr);
  116. break;
  117. }
  118. }
  119. *val = v;
  120. return PCIBIOS_SUCCESSFUL;
  121. }
  122. static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
  123. int size, u32 val)
  124. {
  125. void __iomem *addr = __pci_addr(bus, devfn, where);
  126. int slot = PCI_SLOT(devfn);
  127. if (pci_slot_ignore & (1 << slot)) {
  128. return PCIBIOS_SUCCESSFUL;
  129. }
  130. switch (size) {
  131. case 1:
  132. __raw_writeb((u8)val, addr);
  133. break;
  134. case 2:
  135. __raw_writew((u16)val, addr);
  136. break;
  137. case 4:
  138. __raw_writel(val, addr);
  139. break;
  140. }
  141. return PCIBIOS_SUCCESSFUL;
  142. }
  143. static struct pci_ops pci_versatile_ops = {
  144. .read = versatile_read_config,
  145. .write = versatile_write_config,
  146. };
  147. static struct resource io_mem = {
  148. .name = "PCI I/O space",
  149. .start = VERSATILE_PCI_MEM_BASE0,
  150. .end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
  151. .flags = IORESOURCE_IO,
  152. };
  153. static struct resource non_mem = {
  154. .name = "PCI non-prefetchable",
  155. .start = VERSATILE_PCI_MEM_BASE1,
  156. .end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
  157. .flags = IORESOURCE_MEM,
  158. };
  159. static struct resource pre_mem = {
  160. .name = "PCI prefetchable",
  161. .start = VERSATILE_PCI_MEM_BASE2,
  162. .end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
  163. .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
  164. };
  165. static int __init pci_versatile_setup_resources(struct resource **resource)
  166. {
  167. int ret = 0;
  168. ret = request_resource(&iomem_resource, &io_mem);
  169. if (ret) {
  170. printk(KERN_ERR "PCI: unable to allocate I/O "
  171. "memory region (%d)\n", ret);
  172. goto out;
  173. }
  174. ret = request_resource(&iomem_resource, &non_mem);
  175. if (ret) {
  176. printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
  177. "memory region (%d)\n", ret);
  178. goto release_io_mem;
  179. }
  180. ret = request_resource(&iomem_resource, &pre_mem);
  181. if (ret) {
  182. printk(KERN_ERR "PCI: unable to allocate prefetchable "
  183. "memory region (%d)\n", ret);
  184. goto release_non_mem;
  185. }
  186. /*
  187. * bus->resource[0] is the IO resource for this bus
  188. * bus->resource[1] is the mem resource for this bus
  189. * bus->resource[2] is the prefetch mem resource for this bus
  190. */
  191. resource[0] = &io_mem;
  192. resource[1] = &non_mem;
  193. resource[2] = &pre_mem;
  194. goto out;
  195. release_non_mem:
  196. release_resource(&non_mem);
  197. release_io_mem:
  198. release_resource(&io_mem);
  199. out:
  200. return ret;
  201. }
  202. int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
  203. {
  204. int ret = 0;
  205. int i;
  206. int myslot = -1;
  207. unsigned long val;
  208. void __iomem *local_pci_cfg_base;
  209. val = __raw_readl(SYS_PCICTL);
  210. if (!(val & 1)) {
  211. printk("Not plugged into PCI backplane!\n");
  212. ret = -EIO;
  213. goto out;
  214. }
  215. if (nr == 0) {
  216. sys->mem_offset = 0;
  217. ret = pci_versatile_setup_resources(sys->resource);
  218. if (ret < 0) {
  219. printk("pci_versatile_setup: resources... oops?\n");
  220. goto out;
  221. }
  222. } else {
  223. printk("pci_versatile_setup: resources... nr == 0??\n");
  224. goto out;
  225. }
  226. /*
  227. * We need to discover the PCI core first to configure itself
  228. * before the main PCI probing is performed
  229. */
  230. for (i=0; i<32; i++)
  231. if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
  232. (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
  233. myslot = i;
  234. break;
  235. }
  236. if (myslot == -1) {
  237. printk("Cannot find PCI core!\n");
  238. ret = -EIO;
  239. goto out;
  240. }
  241. printk("PCI core found (slot %d)\n",myslot);
  242. __raw_writel(myslot, PCI_SELFID);
  243. local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
  244. val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
  245. val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
  246. __raw_writel(val, local_pci_cfg_base + CSR_OFFSET);
  247. /*
  248. * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
  249. */
  250. __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
  251. __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
  252. __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
  253. /*
  254. * Do not to map Versatile FPGA PCI device into memory space
  255. */
  256. pci_slot_ignore |= (1 << myslot);
  257. ret = 1;
  258. out:
  259. return ret;
  260. }
  261. struct pci_bus *pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
  262. {
  263. return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
  264. }
  265. void __init pci_versatile_preinit(void)
  266. {
  267. __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
  268. __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
  269. __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
  270. __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
  271. __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
  272. __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);
  273. __raw_writel(1, SYS_PCICTL);
  274. }
  275. /*
  276. * map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
  277. */
  278. static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  279. {
  280. int irq;
  281. int devslot = PCI_SLOT(dev->devfn);
  282. /* slot, pin, irq
  283. * 24 1 27
  284. * 25 1 28
  285. * 26 1 29
  286. * 27 1 30
  287. */
  288. irq = 27 + ((slot + pin - 1) & 3);
  289. printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
  290. return irq;
  291. }
  292. static struct hw_pci versatile_pci __initdata = {
  293. .swizzle = NULL,
  294. .map_irq = versatile_map_irq,
  295. .nr_controllers = 1,
  296. .setup = pci_versatile_setup,
  297. .scan = pci_versatile_scan_bus,
  298. .preinit = pci_versatile_preinit,
  299. };
  300. static int __init versatile_pci_init(void)
  301. {
  302. pci_common_init(&versatile_pci);
  303. return 0;
  304. }
  305. subsys_initcall(versatile_pci_init);