core.c 23 KB

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  1. /*
  2. * linux/arch/arm/mach-versatile/core.c
  3. *
  4. * Copyright (C) 1999 - 2003 ARM Limited
  5. * Copyright (C) 2000 Deep Blue Solutions Ltd
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #include <linux/init.h>
  22. #include <linux/device.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/sysdev.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/amba/bus.h>
  28. #include <linux/amba/clcd.h>
  29. #include <asm/cnt32_to_63.h>
  30. #include <asm/system.h>
  31. #include <asm/hardware.h>
  32. #include <asm/io.h>
  33. #include <asm/irq.h>
  34. #include <asm/leds.h>
  35. #include <asm/hardware/arm_timer.h>
  36. #include <asm/hardware/icst307.h>
  37. #include <asm/hardware/vic.h>
  38. #include <asm/mach-types.h>
  39. #include <asm/mach/arch.h>
  40. #include <asm/mach/flash.h>
  41. #include <asm/mach/irq.h>
  42. #include <asm/mach/time.h>
  43. #include <asm/mach/map.h>
  44. #include <asm/mach/mmc.h>
  45. #include "core.h"
  46. #include "clock.h"
  47. /*
  48. * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  49. * is the (PA >> 12).
  50. *
  51. * Setup a VA for the Versatile Vectored Interrupt Controller.
  52. */
  53. #define __io_address(n) __io(IO_ADDRESS(n))
  54. #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
  55. #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
  56. static void sic_mask_irq(unsigned int irq)
  57. {
  58. irq -= IRQ_SIC_START;
  59. writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  60. }
  61. static void sic_unmask_irq(unsigned int irq)
  62. {
  63. irq -= IRQ_SIC_START;
  64. writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
  65. }
  66. static struct irq_chip sic_chip = {
  67. .name = "SIC",
  68. .ack = sic_mask_irq,
  69. .mask = sic_mask_irq,
  70. .unmask = sic_unmask_irq,
  71. };
  72. static void
  73. sic_handle_irq(unsigned int irq, struct irq_desc *desc)
  74. {
  75. unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
  76. if (status == 0) {
  77. do_bad_IRQ(irq, desc);
  78. return;
  79. }
  80. do {
  81. irq = ffs(status) - 1;
  82. status &= ~(1 << irq);
  83. irq += IRQ_SIC_START;
  84. desc = irq_desc + irq;
  85. desc_handle_irq(irq, desc);
  86. } while (status);
  87. }
  88. #if 1
  89. #define IRQ_MMCI0A IRQ_VICSOURCE22
  90. #define IRQ_AACI IRQ_VICSOURCE24
  91. #define IRQ_ETH IRQ_VICSOURCE25
  92. #define PIC_MASK 0xFFD00000
  93. #else
  94. #define IRQ_MMCI0A IRQ_SIC_MMCI0A
  95. #define IRQ_AACI IRQ_SIC_AACI
  96. #define IRQ_ETH IRQ_SIC_ETH
  97. #define PIC_MASK 0
  98. #endif
  99. void __init versatile_init_irq(void)
  100. {
  101. unsigned int i;
  102. vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
  103. set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
  104. /* Do second interrupt controller */
  105. writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  106. for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
  107. if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
  108. set_irq_chip(i, &sic_chip);
  109. set_irq_handler(i, handle_level_irq);
  110. set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
  111. }
  112. }
  113. /*
  114. * Interrupts on secondary controller from 0 to 8 are routed to
  115. * source 31 on PIC.
  116. * Interrupts from 21 to 31 are routed directly to the VIC on
  117. * the corresponding number on primary controller. This is controlled
  118. * by setting PIC_ENABLEx.
  119. */
  120. writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
  121. }
  122. static struct map_desc versatile_io_desc[] __initdata = {
  123. {
  124. .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
  125. .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
  126. .length = SZ_4K,
  127. .type = MT_DEVICE
  128. }, {
  129. .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
  130. .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
  131. .length = SZ_4K,
  132. .type = MT_DEVICE
  133. }, {
  134. .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
  135. .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
  136. .length = SZ_4K,
  137. .type = MT_DEVICE
  138. }, {
  139. .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
  140. .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
  141. .length = SZ_4K * 9,
  142. .type = MT_DEVICE
  143. },
  144. #ifdef CONFIG_MACH_VERSATILE_AB
  145. {
  146. .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
  147. .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
  148. .length = SZ_4K,
  149. .type = MT_DEVICE
  150. }, {
  151. .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
  152. .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
  153. .length = SZ_64M,
  154. .type = MT_DEVICE
  155. },
  156. #endif
  157. #ifdef CONFIG_DEBUG_LL
  158. {
  159. .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
  160. .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
  161. .length = SZ_4K,
  162. .type = MT_DEVICE
  163. },
  164. #endif
  165. #ifdef CONFIG_PCI
  166. {
  167. .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
  168. .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
  169. .length = SZ_4K,
  170. .type = MT_DEVICE
  171. }, {
  172. .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
  173. .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
  174. .length = VERSATILE_PCI_BASE_SIZE,
  175. .type = MT_DEVICE
  176. }, {
  177. .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
  178. .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
  179. .length = VERSATILE_PCI_CFG_BASE_SIZE,
  180. .type = MT_DEVICE
  181. },
  182. #if 0
  183. {
  184. .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
  185. .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
  186. .length = SZ_16M,
  187. .type = MT_DEVICE
  188. }, {
  189. .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
  190. .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
  191. .length = SZ_16M,
  192. .type = MT_DEVICE
  193. }, {
  194. .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
  195. .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
  196. .length = SZ_16M,
  197. .type = MT_DEVICE
  198. },
  199. #endif
  200. #endif
  201. };
  202. void __init versatile_map_io(void)
  203. {
  204. iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
  205. }
  206. #define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
  207. /*
  208. * This is the Versatile sched_clock implementation. This has
  209. * a resolution of 41.7ns, and a maximum value of about 35583 days.
  210. *
  211. * The return value is guaranteed to be monotonic in that range as
  212. * long as there is always less than 89 seconds between successive
  213. * calls to this function.
  214. */
  215. unsigned long long sched_clock(void)
  216. {
  217. unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
  218. /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
  219. v *= 125<<1;
  220. do_div(v, 3<<1);
  221. return v;
  222. }
  223. #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
  224. static int versatile_flash_init(void)
  225. {
  226. u32 val;
  227. val = __raw_readl(VERSATILE_FLASHCTRL);
  228. val &= ~VERSATILE_FLASHPROG_FLVPPEN;
  229. __raw_writel(val, VERSATILE_FLASHCTRL);
  230. return 0;
  231. }
  232. static void versatile_flash_exit(void)
  233. {
  234. u32 val;
  235. val = __raw_readl(VERSATILE_FLASHCTRL);
  236. val &= ~VERSATILE_FLASHPROG_FLVPPEN;
  237. __raw_writel(val, VERSATILE_FLASHCTRL);
  238. }
  239. static void versatile_flash_set_vpp(int on)
  240. {
  241. u32 val;
  242. val = __raw_readl(VERSATILE_FLASHCTRL);
  243. if (on)
  244. val |= VERSATILE_FLASHPROG_FLVPPEN;
  245. else
  246. val &= ~VERSATILE_FLASHPROG_FLVPPEN;
  247. __raw_writel(val, VERSATILE_FLASHCTRL);
  248. }
  249. static struct flash_platform_data versatile_flash_data = {
  250. .map_name = "cfi_probe",
  251. .width = 4,
  252. .init = versatile_flash_init,
  253. .exit = versatile_flash_exit,
  254. .set_vpp = versatile_flash_set_vpp,
  255. };
  256. static struct resource versatile_flash_resource = {
  257. .start = VERSATILE_FLASH_BASE,
  258. .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
  259. .flags = IORESOURCE_MEM,
  260. };
  261. static struct platform_device versatile_flash_device = {
  262. .name = "armflash",
  263. .id = 0,
  264. .dev = {
  265. .platform_data = &versatile_flash_data,
  266. },
  267. .num_resources = 1,
  268. .resource = &versatile_flash_resource,
  269. };
  270. static struct resource smc91x_resources[] = {
  271. [0] = {
  272. .start = VERSATILE_ETH_BASE,
  273. .end = VERSATILE_ETH_BASE + SZ_64K - 1,
  274. .flags = IORESOURCE_MEM,
  275. },
  276. [1] = {
  277. .start = IRQ_ETH,
  278. .end = IRQ_ETH,
  279. .flags = IORESOURCE_IRQ,
  280. },
  281. };
  282. static struct platform_device smc91x_device = {
  283. .name = "smc91x",
  284. .id = 0,
  285. .num_resources = ARRAY_SIZE(smc91x_resources),
  286. .resource = smc91x_resources,
  287. };
  288. static struct resource versatile_i2c_resource = {
  289. .start = VERSATILE_I2C_BASE,
  290. .end = VERSATILE_I2C_BASE + SZ_4K - 1,
  291. .flags = IORESOURCE_MEM,
  292. };
  293. static struct platform_device versatile_i2c_device = {
  294. .name = "versatile-i2c",
  295. .id = -1,
  296. .num_resources = 1,
  297. .resource = &versatile_i2c_resource,
  298. };
  299. #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
  300. unsigned int mmc_status(struct device *dev)
  301. {
  302. struct amba_device *adev = container_of(dev, struct amba_device, dev);
  303. u32 mask;
  304. if (adev->res.start == VERSATILE_MMCI0_BASE)
  305. mask = 1;
  306. else
  307. mask = 2;
  308. return readl(VERSATILE_SYSMCI) & mask;
  309. }
  310. static struct mmc_platform_data mmc0_plat_data = {
  311. .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
  312. .status = mmc_status,
  313. };
  314. /*
  315. * Clock handling
  316. */
  317. static const struct icst307_params versatile_oscvco_params = {
  318. .ref = 24000,
  319. .vco_max = 200000,
  320. .vd_min = 4 + 8,
  321. .vd_max = 511 + 8,
  322. .rd_min = 1 + 2,
  323. .rd_max = 127 + 2,
  324. };
  325. static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
  326. {
  327. void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
  328. void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
  329. u32 val;
  330. val = readl(sys_osc) & ~0x7ffff;
  331. val |= vco.v | (vco.r << 9) | (vco.s << 16);
  332. writel(0xa05f, sys_lock);
  333. writel(val, sys_osc);
  334. writel(0, sys_lock);
  335. }
  336. static struct clk versatile_clcd_clk = {
  337. .name = "CLCDCLK",
  338. .params = &versatile_oscvco_params,
  339. .setvco = versatile_oscvco_set,
  340. };
  341. /*
  342. * CLCD support.
  343. */
  344. #define SYS_CLCD_MODE_MASK (3 << 0)
  345. #define SYS_CLCD_MODE_888 (0 << 0)
  346. #define SYS_CLCD_MODE_5551 (1 << 0)
  347. #define SYS_CLCD_MODE_565_RLSB (2 << 0)
  348. #define SYS_CLCD_MODE_565_BLSB (3 << 0)
  349. #define SYS_CLCD_NLCDIOON (1 << 2)
  350. #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
  351. #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
  352. #define SYS_CLCD_ID_MASK (0x1f << 8)
  353. #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
  354. #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
  355. #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
  356. #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
  357. #define SYS_CLCD_ID_VGA (0x1f << 8)
  358. static struct clcd_panel vga = {
  359. .mode = {
  360. .name = "VGA",
  361. .refresh = 60,
  362. .xres = 640,
  363. .yres = 480,
  364. .pixclock = 39721,
  365. .left_margin = 40,
  366. .right_margin = 24,
  367. .upper_margin = 32,
  368. .lower_margin = 11,
  369. .hsync_len = 96,
  370. .vsync_len = 2,
  371. .sync = 0,
  372. .vmode = FB_VMODE_NONINTERLACED,
  373. },
  374. .width = -1,
  375. .height = -1,
  376. .tim2 = TIM2_BCD | TIM2_IPC,
  377. .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
  378. .bpp = 16,
  379. };
  380. static struct clcd_panel sanyo_3_8_in = {
  381. .mode = {
  382. .name = "Sanyo QVGA",
  383. .refresh = 116,
  384. .xres = 320,
  385. .yres = 240,
  386. .pixclock = 100000,
  387. .left_margin = 6,
  388. .right_margin = 6,
  389. .upper_margin = 5,
  390. .lower_margin = 5,
  391. .hsync_len = 6,
  392. .vsync_len = 6,
  393. .sync = 0,
  394. .vmode = FB_VMODE_NONINTERLACED,
  395. },
  396. .width = -1,
  397. .height = -1,
  398. .tim2 = TIM2_BCD,
  399. .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
  400. .bpp = 16,
  401. };
  402. static struct clcd_panel sanyo_2_5_in = {
  403. .mode = {
  404. .name = "Sanyo QVGA Portrait",
  405. .refresh = 116,
  406. .xres = 240,
  407. .yres = 320,
  408. .pixclock = 100000,
  409. .left_margin = 20,
  410. .right_margin = 10,
  411. .upper_margin = 2,
  412. .lower_margin = 2,
  413. .hsync_len = 10,
  414. .vsync_len = 2,
  415. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  416. .vmode = FB_VMODE_NONINTERLACED,
  417. },
  418. .width = -1,
  419. .height = -1,
  420. .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
  421. .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
  422. .bpp = 16,
  423. };
  424. static struct clcd_panel epson_2_2_in = {
  425. .mode = {
  426. .name = "Epson QCIF",
  427. .refresh = 390,
  428. .xres = 176,
  429. .yres = 220,
  430. .pixclock = 62500,
  431. .left_margin = 3,
  432. .right_margin = 2,
  433. .upper_margin = 1,
  434. .lower_margin = 0,
  435. .hsync_len = 3,
  436. .vsync_len = 2,
  437. .sync = 0,
  438. .vmode = FB_VMODE_NONINTERLACED,
  439. },
  440. .width = -1,
  441. .height = -1,
  442. .tim2 = TIM2_BCD | TIM2_IPC,
  443. .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
  444. .bpp = 16,
  445. };
  446. /*
  447. * Detect which LCD panel is connected, and return the appropriate
  448. * clcd_panel structure. Note: we do not have any information on
  449. * the required timings for the 8.4in panel, so we presently assume
  450. * VGA timings.
  451. */
  452. static struct clcd_panel *versatile_clcd_panel(void)
  453. {
  454. void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
  455. struct clcd_panel *panel = &vga;
  456. u32 val;
  457. val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
  458. if (val == SYS_CLCD_ID_SANYO_3_8)
  459. panel = &sanyo_3_8_in;
  460. else if (val == SYS_CLCD_ID_SANYO_2_5)
  461. panel = &sanyo_2_5_in;
  462. else if (val == SYS_CLCD_ID_EPSON_2_2)
  463. panel = &epson_2_2_in;
  464. else if (val == SYS_CLCD_ID_VGA)
  465. panel = &vga;
  466. else {
  467. printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
  468. val);
  469. panel = &vga;
  470. }
  471. return panel;
  472. }
  473. /*
  474. * Disable all display connectors on the interface module.
  475. */
  476. static void versatile_clcd_disable(struct clcd_fb *fb)
  477. {
  478. void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
  479. u32 val;
  480. val = readl(sys_clcd);
  481. val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
  482. writel(val, sys_clcd);
  483. #ifdef CONFIG_MACH_VERSATILE_AB
  484. /*
  485. * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
  486. */
  487. if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
  488. void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
  489. unsigned long ctrl;
  490. ctrl = readl(versatile_ib2_ctrl);
  491. ctrl &= ~0x01;
  492. writel(ctrl, versatile_ib2_ctrl);
  493. }
  494. #endif
  495. }
  496. /*
  497. * Enable the relevant connector on the interface module.
  498. */
  499. static void versatile_clcd_enable(struct clcd_fb *fb)
  500. {
  501. void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
  502. u32 val;
  503. val = readl(sys_clcd);
  504. val &= ~SYS_CLCD_MODE_MASK;
  505. switch (fb->fb.var.green.length) {
  506. case 5:
  507. val |= SYS_CLCD_MODE_5551;
  508. break;
  509. case 6:
  510. val |= SYS_CLCD_MODE_565_RLSB;
  511. break;
  512. case 8:
  513. val |= SYS_CLCD_MODE_888;
  514. break;
  515. }
  516. /*
  517. * Set the MUX
  518. */
  519. writel(val, sys_clcd);
  520. /*
  521. * And now enable the PSUs
  522. */
  523. val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
  524. writel(val, sys_clcd);
  525. #ifdef CONFIG_MACH_VERSATILE_AB
  526. /*
  527. * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
  528. */
  529. if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
  530. void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
  531. unsigned long ctrl;
  532. ctrl = readl(versatile_ib2_ctrl);
  533. ctrl |= 0x01;
  534. writel(ctrl, versatile_ib2_ctrl);
  535. }
  536. #endif
  537. }
  538. static unsigned long framesize = SZ_1M;
  539. static int versatile_clcd_setup(struct clcd_fb *fb)
  540. {
  541. dma_addr_t dma;
  542. fb->panel = versatile_clcd_panel();
  543. fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
  544. &dma, GFP_KERNEL);
  545. if (!fb->fb.screen_base) {
  546. printk(KERN_ERR "CLCD: unable to map framebuffer\n");
  547. return -ENOMEM;
  548. }
  549. fb->fb.fix.smem_start = dma;
  550. fb->fb.fix.smem_len = framesize;
  551. return 0;
  552. }
  553. static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
  554. {
  555. return dma_mmap_writecombine(&fb->dev->dev, vma,
  556. fb->fb.screen_base,
  557. fb->fb.fix.smem_start,
  558. fb->fb.fix.smem_len);
  559. }
  560. static void versatile_clcd_remove(struct clcd_fb *fb)
  561. {
  562. dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
  563. fb->fb.screen_base, fb->fb.fix.smem_start);
  564. }
  565. static struct clcd_board clcd_plat_data = {
  566. .name = "Versatile",
  567. .check = clcdfb_check,
  568. .decode = clcdfb_decode,
  569. .disable = versatile_clcd_disable,
  570. .enable = versatile_clcd_enable,
  571. .setup = versatile_clcd_setup,
  572. .mmap = versatile_clcd_mmap,
  573. .remove = versatile_clcd_remove,
  574. };
  575. #define AACI_IRQ { IRQ_AACI, NO_IRQ }
  576. #define AACI_DMA { 0x80, 0x81 }
  577. #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
  578. #define MMCI0_DMA { 0x84, 0 }
  579. #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
  580. #define KMI0_DMA { 0, 0 }
  581. #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
  582. #define KMI1_DMA { 0, 0 }
  583. /*
  584. * These devices are connected directly to the multi-layer AHB switch
  585. */
  586. #define SMC_IRQ { NO_IRQ, NO_IRQ }
  587. #define SMC_DMA { 0, 0 }
  588. #define MPMC_IRQ { NO_IRQ, NO_IRQ }
  589. #define MPMC_DMA { 0, 0 }
  590. #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
  591. #define CLCD_DMA { 0, 0 }
  592. #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
  593. #define DMAC_DMA { 0, 0 }
  594. /*
  595. * These devices are connected via the core APB bridge
  596. */
  597. #define SCTL_IRQ { NO_IRQ, NO_IRQ }
  598. #define SCTL_DMA { 0, 0 }
  599. #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
  600. #define WATCHDOG_DMA { 0, 0 }
  601. #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
  602. #define GPIO0_DMA { 0, 0 }
  603. #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
  604. #define GPIO1_DMA { 0, 0 }
  605. #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
  606. #define RTC_DMA { 0, 0 }
  607. /*
  608. * These devices are connected via the DMA APB bridge
  609. */
  610. #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
  611. #define SCI_DMA { 7, 6 }
  612. #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
  613. #define UART0_DMA { 15, 14 }
  614. #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
  615. #define UART1_DMA { 13, 12 }
  616. #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
  617. #define UART2_DMA { 11, 10 }
  618. #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
  619. #define SSP_DMA { 9, 8 }
  620. /* FPGA Primecells */
  621. AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
  622. AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
  623. AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
  624. AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
  625. /* DevChip Primecells */
  626. AMBA_DEVICE(smc, "dev:00", SMC, NULL);
  627. AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
  628. AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
  629. AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
  630. AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
  631. AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
  632. AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL);
  633. AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
  634. AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
  635. AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
  636. AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
  637. AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
  638. AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
  639. AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
  640. static struct amba_device *amba_devs[] __initdata = {
  641. &dmac_device,
  642. &uart0_device,
  643. &uart1_device,
  644. &uart2_device,
  645. &smc_device,
  646. &mpmc_device,
  647. &clcd_device,
  648. &sctl_device,
  649. &wdog_device,
  650. &gpio0_device,
  651. &gpio1_device,
  652. &rtc_device,
  653. &sci0_device,
  654. &ssp0_device,
  655. &aaci_device,
  656. &mmc0_device,
  657. &kmi0_device,
  658. &kmi1_device,
  659. };
  660. #ifdef CONFIG_LEDS
  661. #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
  662. static void versatile_leds_event(led_event_t ledevt)
  663. {
  664. unsigned long flags;
  665. u32 val;
  666. local_irq_save(flags);
  667. val = readl(VA_LEDS_BASE);
  668. switch (ledevt) {
  669. case led_idle_start:
  670. val = val & ~VERSATILE_SYS_LED0;
  671. break;
  672. case led_idle_end:
  673. val = val | VERSATILE_SYS_LED0;
  674. break;
  675. case led_timer:
  676. val = val ^ VERSATILE_SYS_LED1;
  677. break;
  678. case led_halted:
  679. val = 0;
  680. break;
  681. default:
  682. break;
  683. }
  684. writel(val, VA_LEDS_BASE);
  685. local_irq_restore(flags);
  686. }
  687. #endif /* CONFIG_LEDS */
  688. void __init versatile_init(void)
  689. {
  690. int i;
  691. clk_register(&versatile_clcd_clk);
  692. platform_device_register(&versatile_flash_device);
  693. platform_device_register(&versatile_i2c_device);
  694. platform_device_register(&smc91x_device);
  695. for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
  696. struct amba_device *d = amba_devs[i];
  697. amba_device_register(d, &iomem_resource);
  698. }
  699. #ifdef CONFIG_LEDS
  700. leds_event = versatile_leds_event;
  701. #endif
  702. }
  703. /*
  704. * Where is the timer (VA)?
  705. */
  706. #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
  707. #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
  708. #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
  709. #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
  710. #define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
  711. /*
  712. * How long is the timer interval?
  713. */
  714. #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
  715. #if TIMER_INTERVAL >= 0x100000
  716. #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
  717. #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
  718. #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
  719. #elif TIMER_INTERVAL >= 0x10000
  720. #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
  721. #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
  722. #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
  723. #else
  724. #define TIMER_RELOAD (TIMER_INTERVAL)
  725. #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
  726. #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
  727. #endif
  728. /*
  729. * Returns number of ms since last clock interrupt. Note that interrupts
  730. * will have been disabled by do_gettimeoffset()
  731. */
  732. static unsigned long versatile_gettimeoffset(void)
  733. {
  734. unsigned long ticks1, ticks2, status;
  735. /*
  736. * Get the current number of ticks. Note that there is a race
  737. * condition between us reading the timer and checking for
  738. * an interrupt. We get around this by ensuring that the
  739. * counter has not reloaded between our two reads.
  740. */
  741. ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
  742. do {
  743. ticks1 = ticks2;
  744. status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS);
  745. ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
  746. } while (ticks2 > ticks1);
  747. /*
  748. * Number of ticks since last interrupt.
  749. */
  750. ticks1 = TIMER_RELOAD - ticks2;
  751. /*
  752. * Interrupt pending? If so, we've reloaded once already.
  753. *
  754. * FIXME: Need to check this is effectively timer 0 that expires
  755. */
  756. if (status & IRQMASK_TIMERINT0_1)
  757. ticks1 += TIMER_RELOAD;
  758. /*
  759. * Convert the ticks to usecs
  760. */
  761. return TICKS2USECS(ticks1);
  762. }
  763. /*
  764. * IRQ handler for the timer
  765. */
  766. static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
  767. {
  768. write_seqlock(&xtime_lock);
  769. // ...clear the interrupt
  770. writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
  771. timer_tick();
  772. write_sequnlock(&xtime_lock);
  773. return IRQ_HANDLED;
  774. }
  775. static struct irqaction versatile_timer_irq = {
  776. .name = "Versatile Timer Tick",
  777. .flags = IRQF_DISABLED | IRQF_TIMER,
  778. .handler = versatile_timer_interrupt,
  779. };
  780. /*
  781. * Set up timer interrupt, and return the current time in seconds.
  782. */
  783. static void __init versatile_timer_init(void)
  784. {
  785. u32 val;
  786. /*
  787. * set clock frequency:
  788. * VERSATILE_REFCLK is 32KHz
  789. * VERSATILE_TIMCLK is 1MHz
  790. */
  791. val = readl(__io_address(VERSATILE_SCTL_BASE));
  792. writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
  793. (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
  794. (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
  795. (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
  796. __io_address(VERSATILE_SCTL_BASE));
  797. /*
  798. * Initialise to a known state (all timers off)
  799. */
  800. writel(0, TIMER0_VA_BASE + TIMER_CTRL);
  801. writel(0, TIMER1_VA_BASE + TIMER_CTRL);
  802. writel(0, TIMER2_VA_BASE + TIMER_CTRL);
  803. writel(0, TIMER3_VA_BASE + TIMER_CTRL);
  804. writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
  805. writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
  806. writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
  807. TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
  808. /*
  809. * Make irqs happen for the system timer
  810. */
  811. setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
  812. }
  813. struct sys_timer versatile_timer = {
  814. .init = versatile_timer_init,
  815. .offset = versatile_gettimeoffset,
  816. };