pm-s3c6410.c 18 KB

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  1. /* linux/arch/arm/mach-s3c64xx/pm-s3c6410.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C Power Manager (Suspend-To-RAM) support
  7. *
  8. * 2007.04.19 - Modified by JaeCheol Lee <jc.lee@samsung.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. *
  24. * Parts based on arch/arm/mach-pxa/pm.c
  25. *
  26. * Thanks to Dimitry Andric for debugging
  27. */
  28. #include <linux/config.h>
  29. #include <linux/init.h>
  30. #include <linux/suspend.h>
  31. #include <linux/errno.h>
  32. #include <linux/time.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/crc32.h>
  35. #include <linux/ioport.h>
  36. #include <linux/delay.h>
  37. #include <linux/pm.h>
  38. #include <linux/spinlock.h>
  39. #include <asm/hardware.h>
  40. #include <asm/io.h>
  41. #include <asm/arch/registers.h>
  42. #include <asm/mach/time.h>
  43. #include "pm-s3c6410.h"
  44. /* cache functions from arch/arm/mm/cache-v6.S */
  45. extern void v6_flush_kern_cache_all(void);
  46. /* for external use */
  47. unsigned long s3c_pm_flags;
  48. #define PFX "s3c-pm: "
  49. static struct sleep_save core_save[] = {
  50. SAVE_ITEM(S3C_SDMA_SEL),
  51. };
  52. /* this lot should be really saved by the IRQ code */
  53. /* VICXADDRESSXX initilaization to be needed */
  54. static struct sleep_save irq_save[] = {
  55. SAVE_ITEM(S3C_VIC0INTSELECT),
  56. SAVE_ITEM(S3C_VIC1INTSELECT),
  57. SAVE_ITEM(S3C_VIC0INTENABLE),
  58. SAVE_ITEM(S3C_VIC1INTENABLE),
  59. SAVE_ITEM(S3C_VIC0SOFTINT),
  60. SAVE_ITEM(S3C_VIC1SOFTINT),
  61. };
  62. static struct sleep_save sromc_save[] = {
  63. SAVE_ITEM(S3C_SROM_BW),
  64. SAVE_ITEM(S3C_SROM_BC0),
  65. SAVE_ITEM(S3C_SROM_BC1),
  66. SAVE_ITEM(S3C_SROM_BC2),
  67. SAVE_ITEM(S3C_SROM_BC3),
  68. SAVE_ITEM(S3C_SROM_BC4),
  69. SAVE_ITEM(S3C_SROM_BC5),
  70. };
  71. static struct sleep_save gpio_save[] = {
  72. SAVE_ITEM(S3C_GPK0CON),
  73. SAVE_ITEM(S3C_GPK1CON),
  74. SAVE_ITEM(S3C_GPKDAT),
  75. SAVE_ITEM(S3C_GPKPU),
  76. SAVE_ITEM(S3C_GPL0CON),
  77. SAVE_ITEM(S3C_GPL1CON),
  78. SAVE_ITEM(S3C_GPLDAT),
  79. SAVE_ITEM(S3C_GPLPU),
  80. SAVE_ITEM(S3C_GPMCON),
  81. SAVE_ITEM(S3C_GPMDAT),
  82. SAVE_ITEM(S3C_GPMPU),
  83. SAVE_ITEM(S3C_GPNCON),
  84. SAVE_ITEM(S3C_GPNDAT),
  85. SAVE_ITEM(S3C_GPNPU),
  86. /* External interrupt */
  87. SAVE_ITEM(S3C_EINTCON0),
  88. SAVE_ITEM(S3C_EINTCON1),
  89. SAVE_ITEM(S3C_EINTFLTCON0),
  90. SAVE_ITEM(S3C_EINTFLTCON1),
  91. SAVE_ITEM(S3C_EINTFLTCON2),
  92. SAVE_ITEM(S3C_EINTFLTCON3),
  93. SAVE_ITEM(S3C_EINTMASK),
  94. SAVE_ITEM(S3C_EINT12CON),
  95. SAVE_ITEM(S3C_EINT34CON),
  96. SAVE_ITEM(S3C_EINT56CON),
  97. SAVE_ITEM(S3C_EINT78CON),
  98. SAVE_ITEM(S3C_EINT9CON),
  99. SAVE_ITEM(S3C_EINT12FLTCON),
  100. SAVE_ITEM(S3C_EINT34FLTCON),
  101. SAVE_ITEM(S3C_EINT56FLTCON),
  102. SAVE_ITEM(S3C_EINT78FLTCON),
  103. SAVE_ITEM(S3C_EINT9FLTCON),
  104. SAVE_ITEM(S3C_EINT12MASK),
  105. SAVE_ITEM(S3C_EINT34MASK),
  106. SAVE_ITEM(S3C_EINT56MASK),
  107. SAVE_ITEM(S3C_EINT78MASK),
  108. SAVE_ITEM(S3C_EINT9MASK),
  109. SAVE_ITEM(S3C_EINT34FLTCON),
  110. SAVE_ITEM(S3C_EINT56FLTCON),
  111. SAVE_ITEM(S3C_EINT78FLTCON),
  112. SAVE_ITEM(S3C_EINT9FLTCON),
  113. SAVE_ITEM(S3C_PRIORITY),
  114. /* GPIO memory map bug in EVT0 */
  115. SAVE_ITEM(S3C_GPACON),
  116. SAVE_ITEM(S3C_GPADAT),
  117. SAVE_ITEM(S3C_GPAPU),
  118. SAVE_ITEM(S3C_GPBCON),
  119. SAVE_ITEM(S3C_GPBDAT),
  120. SAVE_ITEM(S3C_GPBPU),
  121. SAVE_ITEM(S3C_GPCCON),
  122. SAVE_ITEM(S3C_GPCDAT),
  123. SAVE_ITEM(S3C_GPCPU),
  124. SAVE_ITEM(S3C_GPDCON),
  125. SAVE_ITEM(S3C_GPDDAT),
  126. SAVE_ITEM(S3C_GPDPU),
  127. SAVE_ITEM(S3C_GPECON),
  128. SAVE_ITEM(S3C_GPEDAT),
  129. SAVE_ITEM(S3C_GPEPU),
  130. SAVE_ITEM(S3C_GPFCON),
  131. SAVE_ITEM(S3C_GPFDAT),
  132. SAVE_ITEM(S3C_GPFPU),
  133. SAVE_ITEM(S3C_GPGCON),
  134. SAVE_ITEM(S3C_GPGDAT),
  135. SAVE_ITEM(S3C_GPGPU),
  136. SAVE_ITEM(S3C_GPH0CON),
  137. SAVE_ITEM(S3C_GPH1CON),
  138. SAVE_ITEM(S3C_GPHDAT),
  139. SAVE_ITEM(S3C_GPHPU),
  140. SAVE_ITEM(S3C_GPICON),
  141. SAVE_ITEM(S3C_GPIDAT),
  142. SAVE_ITEM(S3C_GPIPU),
  143. SAVE_ITEM(S3C_GPJCON),
  144. SAVE_ITEM(S3C_GPJDAT),
  145. SAVE_ITEM(S3C_GPJPU),
  146. SAVE_ITEM(S3C_GPOCON),
  147. SAVE_ITEM(S3C_GPODAT),
  148. SAVE_ITEM(S3C_GPOPU),
  149. SAVE_ITEM(S3C_GPPCON),
  150. SAVE_ITEM(S3C_GPPDAT),
  151. SAVE_ITEM(S3C_GPPPU),
  152. SAVE_ITEM(S3C_GPQCON),
  153. SAVE_ITEM(S3C_GPQDAT),
  154. SAVE_ITEM(S3C_GPQPU),
  155. /* Special register*/
  156. SAVE_ITEM(S3C_SPCON),
  157. /* Memory port control */
  158. SAVE_ITEM(S3C_MEM0CONSTOP),
  159. SAVE_ITEM(S3C_MEM1CONSTOP),
  160. SAVE_ITEM(S3C_MEM0CONSLP0),
  161. SAVE_ITEM(S3C_MEM0CONSLP1),
  162. SAVE_ITEM(S3C_MEM1CONSLP),
  163. SAVE_ITEM(S3C_MEM0DRVCON),
  164. SAVE_ITEM(S3C_MEM1DRVCON),
  165. };
  166. static struct sleep_save ts_save[] = {
  167. /* Touch Screen */
  168. SAVE_ITEM(S3C_ADCDLY),
  169. SAVE_ITEM(S3C_ADCTSC),
  170. SAVE_ITEM(S3C_ADCCON),
  171. };
  172. static struct sleep_save lcd_save[] = {
  173. };
  174. #define SAVE_UART(va) \
  175. SAVE_ITEM((va) + S3C_ULCON), \
  176. SAVE_ITEM((va) + S3C_UCON), \
  177. SAVE_ITEM((va) + S3C_UFCON), \
  178. SAVE_ITEM((va) + S3C_UMCON), \
  179. SAVE_ITEM((va) + S3C_UBRDIV), \
  180. SAVE_ITEM((va) + S3C_UDIVSLOT), \
  181. SAVE_ITEM((va) + S3C_UINTMSK)
  182. static struct sleep_save uart_save[] = {
  183. SAVE_UART(S3C24XX_VA_UART0),
  184. SAVE_UART(S3C24XX_VA_UART1),
  185. SAVE_UART(S3C24XX_VA_UART2),
  186. SAVE_UART(S3C24XX_VA_UART3),
  187. };
  188. #if 1
  189. /* debug
  190. *
  191. * we send the debug to printascii() to allow it to be seen if the
  192. * system never wakes up from the sleep
  193. */
  194. extern void printascii(const char *);
  195. static void pm_dbg(const char *fmt, ...)
  196. {
  197. va_list va;
  198. char buff[256];
  199. va_start(va, fmt);
  200. vsprintf(buff, fmt, va);
  201. va_end(va);
  202. printascii(buff);
  203. }
  204. static void s3c6400_pm_debug_init(void)
  205. {
  206. unsigned long tmp = __raw_readl(S3C_PCLK_GATE);
  207. /* re-start uart clocks */
  208. tmp |= S3C_CLKCON_PCLK_UART0;
  209. tmp |= S3C_CLKCON_PCLK_UART1;
  210. tmp |= S3C_CLKCON_PCLK_UART2;
  211. __raw_writel(tmp, S3C_PCLK_GATE);
  212. udelay(10);
  213. }
  214. #define DBG(fmt...) pm_dbg(fmt)
  215. #else
  216. #define DBG(fmt...) printk(KERN_DEBUG fmt)
  217. #define s3c6400_pm_debug_init() do { } while(0)
  218. #endif
  219. #if defined(CONFIG_S3C6400_PM_CHECK) && CONFIG_S3C6400_PM_CHECK_CHUNKSIZE != 0
  220. /* suspend checking code...
  221. *
  222. * this next area does a set of crc checks over all the installed
  223. * memory, so the system can verify if the resume was ok.
  224. *
  225. * CONFIG_S3C6400_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
  226. * increasing it will mean that the area corrupted will be less easy to spot,
  227. * and reducing the size will cause the CRC save area to grow
  228. */
  229. #define CHECK_CHUNKSIZE (CONFIG_S3C6400_PM_CHECK_CHUNKSIZE * 1024)
  230. static u32 crc_size; /* size needed for the crc block */
  231. static u32 *crcs; /* allocated over suspend/resume */
  232. typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
  233. /* s3c6400_pm_run_res
  234. *
  235. * go thorugh the given resource list, and look for system ram
  236. */
  237. static void s3c6400_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
  238. {
  239. while (ptr != NULL) {
  240. if (ptr->child != NULL)
  241. s3c6400_pm_run_res(ptr->child, fn, arg);
  242. if ((ptr->flags & IORESOURCE_MEM) &&
  243. strcmp(ptr->name, "System RAM") == 0) {
  244. DBG("Found system RAM at %08lx..%08lx\n",
  245. ptr->start, ptr->end);
  246. arg = (fn)(ptr, arg);
  247. }
  248. ptr = ptr->sibling;
  249. }
  250. }
  251. static void s3c6400_pm_run_sysram(run_fn_t fn, u32 *arg)
  252. {
  253. s3c6400_pm_run_res(&iomem_resource, fn, arg);
  254. }
  255. static u32 *s3c6400_pm_countram(struct resource *res, u32 *val)
  256. {
  257. u32 size = (u32)(res->end - res->start)+1;
  258. size += CHECK_CHUNKSIZE-1;
  259. size /= CHECK_CHUNKSIZE;
  260. DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
  261. *val += size * sizeof(u32);
  262. return val;
  263. }
  264. /* s3c6400_pm_prepare_check
  265. *
  266. * prepare the necessary information for creating the CRCs. This
  267. * must be done before the final save, as it will require memory
  268. * allocating, and thus touching bits of the kernel we do not
  269. * know about.
  270. */
  271. static void s3c6400_pm_check_prepare(void)
  272. {
  273. crc_size = 0;
  274. s3c6400_pm_run_sysram(s3c6400_pm_countram, &crc_size);
  275. DBG("s3c6400_pm_prepare_check: %u checks needed\n", crc_size);
  276. crcs = kmalloc(crc_size+4, GFP_KERNEL);
  277. if (crcs == NULL)
  278. printk(KERN_ERR "Cannot allocated CRC save area\n");
  279. }
  280. static u32 *s3c6400_pm_makecheck(struct resource *res, u32 *val)
  281. {
  282. unsigned long addr, left;
  283. for (addr = res->start; addr < res->end;
  284. addr += CHECK_CHUNKSIZE) {
  285. left = res->end - addr;
  286. if (left > CHECK_CHUNKSIZE)
  287. left = CHECK_CHUNKSIZE;
  288. *val = crc32_le(~0, phys_to_virt(addr), left);
  289. val++;
  290. }
  291. return val;
  292. }
  293. /* s3c6400_pm_check_store
  294. *
  295. * compute the CRC values for the memory blocks before the final
  296. * sleep.
  297. */
  298. static void s3c6400_pm_check_store(void)
  299. {
  300. if (crcs != NULL)
  301. s3c6400_pm_run_sysram(s3c6400_pm_makecheck, crcs);
  302. }
  303. /* in_region
  304. *
  305. * return TRUE if the area defined by ptr..ptr+size contatins the
  306. * what..what+whatsz
  307. */
  308. static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
  309. {
  310. if ((what+whatsz) < ptr)
  311. return 0;
  312. if (what > (ptr+size))
  313. return 0;
  314. return 1;
  315. }
  316. static u32 *s3c6400_pm_runcheck(struct resource *res, u32 *val)
  317. {
  318. void *save_at = phys_to_virt(s3c6400_sleep_save_phys);
  319. unsigned long addr;
  320. unsigned long left;
  321. void *ptr;
  322. u32 calc;
  323. for (addr = res->start; addr < res->end;
  324. addr += CHECK_CHUNKSIZE) {
  325. left = res->end - addr;
  326. if (left > CHECK_CHUNKSIZE)
  327. left = CHECK_CHUNKSIZE;
  328. ptr = phys_to_virt(addr);
  329. if (in_region(ptr, left, crcs, crc_size)) {
  330. DBG("skipping %08lx, has crc block in\n", addr);
  331. goto skip_check;
  332. }
  333. if (in_region(ptr, left, save_at, 32*4 )) {
  334. DBG("skipping %08lx, has save block in\n", addr);
  335. goto skip_check;
  336. }
  337. /* calculate and check the checksum */
  338. calc = crc32_le(~0, ptr, left);
  339. if (calc != *val) {
  340. printk(KERN_ERR PFX "Restore CRC error at "
  341. "%08lx (%08x vs %08x)\n", addr, calc, *val);
  342. DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
  343. addr, calc, *val);
  344. }
  345. skip_check:
  346. val++;
  347. }
  348. return val;
  349. }
  350. /* s3c6400_pm_check_restore
  351. *
  352. * check the CRCs after the restore event and free the memory used
  353. * to hold them
  354. */
  355. static void s3c6400_pm_check_restore(void)
  356. {
  357. if (crcs != NULL) {
  358. s3c6400_pm_run_sysram(s3c6400_pm_runcheck, crcs);
  359. kfree(crcs);
  360. crcs = NULL;
  361. }
  362. }
  363. #else
  364. #define s3c6400_pm_check_prepare() do { } while(0)
  365. #define s3c6400_pm_check_restore() do { } while(0)
  366. #define s3c6400_pm_check_store() do { } while(0)
  367. #endif
  368. /* helper functions to save and restore register state */
  369. void s3c6400_pm_do_save(struct sleep_save *ptr, int count)
  370. {
  371. for (; count > 0; count--, ptr++) {
  372. ptr->val = __raw_readl(ptr->reg);
  373. // DBG("saved %08lx value %08lx\n", ptr->reg, ptr->val);
  374. }
  375. }
  376. /* s3c6400_pm_do_restore
  377. *
  378. * restore the system from the given list of saved registers
  379. *
  380. * Note, we do not use DBG() in here, as the system may not have
  381. * restore the UARTs state yet
  382. */
  383. void s3c6400_pm_do_restore(struct sleep_save *ptr, int count)
  384. {
  385. for (; count > 0; count--, ptr++) {
  386. // printk(KERN_DEBUG "restore %08lx (restore %08lx, was %08x)\n",
  387. // ptr->reg, ptr->val, __raw_readl(ptr->reg));
  388. __raw_writel(ptr->val, ptr->reg);
  389. }
  390. }
  391. /* s3c6400_pm_do_restore_core
  392. *
  393. * similar to s3c6400_pm_do_restore_core
  394. *
  395. * WARNING: Do not put any debug in here that may effect memory or use
  396. * peripherals, as things may be changing!
  397. */
  398. static void s3c6400_pm_do_restore_core(struct sleep_save *ptr, int count)
  399. {
  400. for (; count > 0; count--, ptr++) {
  401. __raw_writel(ptr->val, ptr->reg);
  402. }
  403. }
  404. /* s3c6400_pm_show_resume_irqs
  405. *
  406. * print any IRQs asserted at resume time (ie, we woke from)
  407. */
  408. static void s3c6400_pm_show_resume_irqs(int start, unsigned long which,
  409. unsigned long mask)
  410. {
  411. }
  412. /* s3c6400_pm_check_resume_pin
  413. *
  414. * check to see if the pin is configured correctly for sleep mode, and
  415. * make any necessary adjustments if it is not
  416. */
  417. static void s3c6400_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
  418. {
  419. }
  420. /* s3c6400_pm_configure_extint
  421. *
  422. * configure all external interrupt pins
  423. */
  424. static void s3c6400_pm_configure_extint(void)
  425. {
  426. __raw_writel(0xfffffff, S3C_EINTMASK);
  427. // __raw_writel(0xaaaaaaaa, S3C_GPNCON); // Set EINT configuration
  428. // __raw_writel(0x0, S3C_EINTCON0); // Low level detecting (EINT0~15)
  429. // __raw_writel(0x0, S3C_EINTCON1); // Low level detecting (EINT16~27)
  430. #if 0
  431. __raw_writel(__raw_readl(S3C_EINTPEND), S3C_EINTPEND); // All EINT pending clear
  432. do {
  433. __raw_writel(__raw_readl(S3C_EINTPEND), S3C_EINTPEND); // All EINT pending clear
  434. } while(__raw_readl(S3C_EINTPEND));
  435. #endif
  436. }
  437. static void s3c6400_pm_config_gpio(void)
  438. {
  439. /* To reset HS-MMC GPIO */
  440. __raw_writel(0x0, S3C_GPGCON);
  441. }
  442. static inline void s3c6400_poweroff_misc(void)
  443. {
  444. unsigned int temp;
  445. __raw_writel(0x0, S3C_RTCCON);
  446. temp = __raw_readl(S3C_ADCCON);
  447. __raw_writel(temp |(1<<2), S3C_ADCCON);
  448. // USB Power Control
  449. temp = __raw_readl(S3C_SPCON);
  450. __raw_writel(temp|(1<<3), S3C_SPCON);
  451. temp = __raw_readl(S3C_OTHERS);
  452. __raw_writel(temp|(1<<14), S3C_OTHERS);
  453. }
  454. void s3c6400_setup_keypad_wakeup(void)
  455. {
  456. }
  457. void s3c6400_setup_rtc_wakeup(void)
  458. {
  459. #define TESTYEAR (0x5)
  460. #define TESTMONTH (0x12)
  461. #define TESTDATE (0x31)
  462. #define TESTDAY (0x7)
  463. #define TESTHOUR (0x23)
  464. #define TESTMIN (0x59)
  465. #define TESTSEC (0x59)
  466. #define TESTYEAR2 (0x6)
  467. #define TESTMONTH2 (0x1)
  468. #define TESTDATE2 (0x1)
  469. #define TESTHOUR2 (0x0)
  470. #define TESTMIN2 (0x0)
  471. #define TESTSEC2 (0x0)
  472. __raw_writel(1,S3C_RTCCON);
  473. __raw_writel(TESTYEAR,S3C_RTCYEAR);
  474. __raw_writel(TESTMONTH,S3C_RTCMON);
  475. __raw_writel(TESTDATE,S3C_RTCDATE);
  476. __raw_writel(TESTDAY,S3C_RTCDAY);
  477. __raw_writel(TESTHOUR,S3C_RTCHOUR);
  478. __raw_writel(TESTMIN,S3C_RTCMIN);
  479. __raw_writel(TESTSEC,S3C_RTCSEC);
  480. __raw_writel(TESTYEAR2,S3C_ALMYEAR);
  481. __raw_writel(TESTMONTH2,S3C_ALMMON);
  482. __raw_writel(TESTDATE2,S3C_ALMDATE);
  483. __raw_writel(TESTHOUR2,S3C_ALMHOUR);
  484. __raw_writel(TESTMIN2,S3C_ALMMIN);
  485. __raw_writel((TESTSEC2 + 0x10),S3C_ALMSEC);
  486. __raw_writel(0x7f,S3C_RTCALM);
  487. __raw_writel(0,S3C_RTCCON);
  488. }
  489. unsigned long sleep_phys_sp(void *sp)
  490. {
  491. return virt_to_phys(sp);
  492. }
  493. #define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
  494. /* s3c6400_pm_enter
  495. *
  496. * central control for sleep/resume process
  497. */
  498. static int s3c6400_pm_enter(suspend_state_t state)
  499. {
  500. unsigned long regs_save[16];
  501. unsigned long clkcon, irqindex = 0;
  502. unsigned int pwr_cfg, sleep_cfg, normal_cfg, hclk_gate, temp, irqno;
  503. /* ensure the debug is initialised (if enabled) */
  504. // s3c6400_pm_debug_init();
  505. if (state != PM_SUSPEND_MEM) {
  506. printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n");
  507. return -EINVAL;
  508. }
  509. /* prepare check area if configured */
  510. s3c6400_pm_check_prepare();
  511. /* store the physical address of the register recovery block */
  512. s3c6400_sleep_save_phys = virt_to_phys(regs_save);
  513. printk("s3c6400_sleep_save_phys=0x%08lx\n", s3c6400_sleep_save_phys);
  514. /* save all necessary core registers not covered by the drivers */
  515. s3c6400_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
  516. s3c6400_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
  517. s3c6400_pm_do_save(core_save, ARRAY_SIZE(core_save));
  518. s3c6400_pm_do_save(sromc_save, ARRAY_SIZE(sromc_save));
  519. s3c6400_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
  520. s3c6400_pm_do_save(lcd_save, ARRAY_SIZE(lcd_save));
  521. s3c6400_pm_do_save(ts_save, ARRAY_SIZE(ts_save));
  522. /* ensure INF_REG0 has the resume address */
  523. __raw_writel(virt_to_phys(s3c6400_cpu_resume), S3C_INFORM0);
  524. /* set the irq configuration for wake */
  525. s3c6400_pm_configure_extint();
  526. s3c6400_poweroff_misc();
  527. s3c6400_pm_config_gpio();
  528. s3c6400_pm_check_store();
  529. __raw_writel(0xffffffff, S3C_VIC0INTENCLEAR);
  530. __raw_writel(0xffffffff, S3C_VIC1INTENCLEAR);
  531. __raw_writel(0xffffffff, S3C_VIC0SOFTINTCLEAR);
  532. __raw_writel(0xffffffff, S3C_VIC1SOFTINTCLEAR);
  533. s3c6400_setup_keypad_wakeup();
  534. // s3c6400_setup_rtc_wakeup();
  535. __raw_writel(1, S3C_OSC_STABLE);
  536. __raw_writel(1, S3C_PWR_STABLE);
  537. /* Set WFI instruction to SLEEP mode */
  538. pwr_cfg = __raw_readl(S3C_PWR_CFG);
  539. pwr_cfg &= ~(0x60<<0);
  540. pwr_cfg |= (0x3<<5);
  541. __raw_writel(pwr_cfg, S3C_PWR_CFG);
  542. sleep_cfg = __raw_readl(S3C_SLEEP_CFG);
  543. sleep_cfg &= ~(0x61<<0);
  544. __raw_writel(sleep_cfg, S3C_SLEEP_CFG);
  545. __raw_writel((0x0fffffff&~(1<<9)), S3C_EINT_MASK);
  546. __raw_writel(0x2, S3C_SLPEN);
  547. /* ALL sub block "ON" before enterring sleep mode - EVT0 bug*/
  548. __raw_writel(0xffffff00, S3C_NORMAL_CFG);
  549. /* Open all clock gate to enter sleep mode - EVT0 bug*/
  550. __raw_writel(0xffffffff, S3C_HCLK_GATE);
  551. __raw_writel(0xffffffff, S3C_PCLK_GATE);
  552. __raw_writel(0xffffffff, S3C_SCLK_GATE);
  553. s3c6400_cpu_suspend(regs_save);
  554. /* restore the cpu state */
  555. cpu_init();
  556. /* restore the system state */
  557. s3c6400_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
  558. s3c6400_pm_do_restore(sromc_save, ARRAY_SIZE(sromc_save));
  559. s3c6400_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
  560. s3c6400_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
  561. s3c6400_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
  562. s3c6400_pm_do_restore(lcd_save, ARRAY_SIZE(lcd_save));
  563. s3c6400_pm_do_restore(ts_save, ARRAY_SIZE(ts_save));
  564. temp = __raw_readl(S3C_EINTPEND);
  565. __raw_writel(temp, S3C_EINTPEND);
  566. /* For writing the IRQ number into the VICVECTADDR */
  567. for (irqno = IRQ_EINT0_3; irqno <= IRQ_LCD_SYSTEM; irqno++) {
  568. __raw_writel(irqno, S3C_VIC0VECTADDR0 + irqindex);
  569. irqindex = irqindex + 4;
  570. }
  571. irqindex = 0;
  572. for (irqno = IRQ_EINT12_19; irqno <= IRQ_ADC; irqno++) {
  573. __raw_writel(irqno, S3C_VIC1VECTADDR0 + irqindex);
  574. irqindex = irqindex + 4;
  575. }
  576. s3c6400_pm_debug_init();
  577. DBG("post sleep, preparing to return\n");
  578. s3c6400_pm_check_restore();
  579. /* ok, let's return from sleep */
  580. DBG("S3C6400 PM Resume (post-restore)\n");
  581. return 0;
  582. }
  583. /*
  584. * Called after processes are frozen, but before we shut down devices.
  585. */
  586. static int s3c6400_pm_prepare(suspend_state_t state)
  587. {
  588. printk(" preparing for pwrdown\n");
  589. return 0;
  590. }
  591. /*
  592. * Called after devices are re-setup, but before processes are thawed.
  593. */
  594. static int s3c6400_pm_finish(suspend_state_t state)
  595. {
  596. return 0;
  597. }
  598. /*
  599. * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
  600. */
  601. static struct pm_ops s3c6400_pm_ops = {
  602. .pm_disk_mode = PM_DISK_FIRMWARE,
  603. .prepare = s3c6400_pm_prepare,
  604. .enter = s3c6400_pm_enter,
  605. .finish = s3c6400_pm_finish,
  606. };
  607. int __init s3c6400_pm_init(void)
  608. {
  609. printk("S3C6400 Power Management, (c) 2006 Samsung Electronics\n");
  610. enable_irq_wake(IRQ_EINT9);
  611. enable_irq_wake(IRQ_RTC_ALARM);
  612. pm_set_ops(&s3c6400_pm_ops);
  613. return 0;
  614. }
  615. module_init(s3c6400_pm_init);