mach-smdk6430.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569
  1. /***********************************************************************
  2. *
  3. * linux/arch/arm/mach-s3c6410/mach-smdk6410.c
  4. *
  5. * $Id: mach-smdk6430.c,v 1.2 2008/07/14 00:19:02 wizardsj Exp $
  6. *
  7. * Copyright (C) 2005, Sean Choi <sh428.choi@samsung.com>
  8. * All rights reserved
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. *
  25. * derived from linux/arch/arm/mach-s3c2410/devs.c, written by
  26. * Ben Dooks <ben@simtec.co.uk>
  27. *
  28. ***********************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/types.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/list.h>
  33. #include <linux/timer.h>
  34. #include <linux/init.h>
  35. #include <linux/delay.h>
  36. #include <linux/platform_device.h>
  37. #include <linux/mtd/mtd.h>
  38. #include <linux/mtd/partitions.h>
  39. #include <asm/setup.h>
  40. #include <asm/mach/arch.h>
  41. #include <asm/mach/map.h>
  42. #include <asm/mach/irq.h>
  43. #include <asm/mach/flash.h>
  44. #include <asm/hardware.h>
  45. #include <asm/io.h>
  46. #include <asm/irq.h>
  47. #include <asm/mach-types.h>
  48. #include <asm/arch/regs-serial.h>
  49. #include <asm/arch/regs-gpio.h>
  50. #include <asm/arch/regs-mem.h>
  51. #include <asm/arch/regs-s3c6410-clock.h>
  52. #include <asm/arch/nand.h>
  53. #include <asm/plat-s3c24xx/s3c6400.h>
  54. #include <asm/plat-s3c24xx/devs.h>
  55. #include <asm/plat-s3c24xx/cpu.h>
  56. #include <asm/arch/hsmmc.h>
  57. #include <asm/plat-s3c24xx/common-smdk.h>
  58. #include <asm/arch-s3c2410/reserved_mem.h>
  59. #if defined(CONFIG_MACH_SANJOSE2)
  60. #include <asm/arch/regs-irq.h>
  61. #endif
  62. extern struct sys_timer s3c_timer;
  63. static struct map_desc smdk6410_iodesc[] __initdata = {
  64. IODESC_ENT(CS8900),
  65. };
  66. #define DEF_UCON S3C_UCON_DEFAULT
  67. #define DEF_ULCON S3C_LCON_CS8 | S3C_LCON_PNONE
  68. #define DEF_UFCON S3C_UFCON_RXTRIG8 | S3C_UFCON_FIFOMODE
  69. static struct s3c24xx_uart_clksrc smdk6410_serial_clocks[] = {
  70. /* UART Clock with MPLL by Boyko */
  71. [0] = {
  72. .name = "mpll_clk_uart",
  73. .divisor = 1,
  74. .min_baud = 0,
  75. .max_baud = 0,
  76. },
  77. #if 0 /* HS UART Source is changed from epll to mpll */
  78. [1] = {
  79. .name = "pclk",
  80. .divisor = 1,
  81. .min_baud = 0,
  82. .max_baud = 0,
  83. },
  84. #if defined (CONFIG_SERIAL_S3C64XX_HS_UART)
  85. [2] = {
  86. .name = "epll_clk_uart_192m",
  87. .divisor = 1,
  88. .min_baud = 0,
  89. .max_baud = 4000000,
  90. }
  91. #endif
  92. #endif
  93. };
  94. static struct s3c2410_uartcfg smdk6410_uartcfgs[] = {
  95. [0] = {
  96. .hwport = 0,
  97. .flags = 0,
  98. .ucon = DEF_UCON,
  99. .ulcon = DEF_ULCON,
  100. .ufcon = DEF_UFCON,
  101. .clocks = smdk6410_serial_clocks,
  102. .clocks_size = ARRAY_SIZE(smdk6410_serial_clocks),
  103. },
  104. [1] = {
  105. .hwport = 1,
  106. .flags = 0,
  107. .ucon = DEF_UCON,
  108. .ulcon = DEF_ULCON,
  109. .ufcon = DEF_UFCON,
  110. .clocks = smdk6410_serial_clocks,
  111. .clocks_size = ARRAY_SIZE(smdk6410_serial_clocks),
  112. },
  113. [2] = {
  114. .hwport = 2,
  115. .flags = 0,
  116. .ucon = DEF_UCON,
  117. .ulcon = DEF_ULCON,
  118. .ufcon = DEF_UFCON,
  119. .clocks = smdk6410_serial_clocks,
  120. .clocks_size = ARRAY_SIZE(smdk6410_serial_clocks),
  121. },
  122. [3] = {
  123. .hwport = 3,
  124. .flags = 0,
  125. .ucon = DEF_UCON,
  126. .ulcon = DEF_ULCON,
  127. .ufcon = DEF_UFCON,
  128. .clocks = smdk6410_serial_clocks,
  129. .clocks_size = ARRAY_SIZE(smdk6410_serial_clocks),
  130. }
  131. };
  132. /*add devices as drivers are integrated*/
  133. static struct platform_device *smdk6410_devices[] __initdata = {
  134. &s3c_device_lcd,
  135. &s3c_device_rtc,
  136. &s3c_device_ac97,
  137. &s3c_device_iis,
  138. &s3c_device_adc,
  139. &s3c_device_i2c,
  140. &s3c_device_usb,
  141. &s3c_device_usbgadget,
  142. &s3c_device_tvenc,
  143. &s3c_device_tvscaler,
  144. &s3c_device_hsmmc0,
  145. &s3c_device_hsmmc1,
  146. &s3c_device_hsmmc2,
  147. &s3c_device_wdt,
  148. &s3c_device_jpeg,
  149. &s3c_device_vpp,
  150. &s3c_device_ide,
  151. // &s3c_device_mfc,
  152. &s3c_device_spi0,
  153. &s3c_device_spi1,
  154. &s3c_device_camif,
  155. &s3c_device_2d,
  156. &s3c_device_keypad,
  157. // &s3c_device_g3d,
  158. &s3c_device_smc911x,
  159. &s3c_device_rotator,
  160. &s3c_device_iis_v40,
  161. };
  162. static struct s3c24xx_board smdk6410_board __initdata = {
  163. .devices = smdk6410_devices,
  164. .devices_count = ARRAY_SIZE(smdk6410_devices)
  165. };
  166. static void __init smdk6410_map_io(void)
  167. {
  168. s3c24xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
  169. s3c24xx_init_clocks(0);
  170. s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
  171. s3c24xx_set_board(&smdk6410_board);
  172. }
  173. void smdk6410_cs89x0_set(void)
  174. {
  175. unsigned int tmp;
  176. tmp = __raw_readl(S3C_SROM_BW);
  177. tmp &=~(0xF<<4);
  178. tmp |= (1<<7) | (1<<6) | (1<<4);
  179. __raw_writel(tmp, S3C_SROM_BW);
  180. __raw_writel((0x0<<28)|(0x4<<24)|(0xd<<16)|(0x1<<12)|(0x4<<8)|(0x6<<4)|(0x0<<0), S3C_SROM_BC1);
  181. #if defined(CONFIG_MACH_SANJOSE2)
  182. __raw_writel(0, S3C_GPPPU);
  183. __raw_writel((__raw_readl(S3C_GPPCON) & ~(0x3 << 14)) | (0x1 << 14), S3C_GPPCON);
  184. #endif
  185. }
  186. static void __init smdk6410_fixup (struct machine_desc *desc, struct tag *tags,
  187. char **cmdline, struct meminfo *mi)
  188. {
  189. /*
  190. * Bank start addresses are not present in the information
  191. * passed in from the boot loader. We could potentially
  192. * detect them, but instead we hard-code them.
  193. */
  194. mi->bank[0].start = 0x50000000;
  195. #if defined(CONFIG_RESERVED_MEM_JPEG)
  196. mi->bank[0].size = 120*1024*1024;
  197. #elif defined(CONFIG_RESERVED_MEM_JPEG_POST)
  198. mi->bank[0].size = 112*1024*1024;
  199. #elif defined(CONFIG_RESERVED_MEM_MFC)
  200. mi->bank[0].size = 122*1024*1024;
  201. #elif defined(CONFIG_RESERVED_MEM_MFC_POST)
  202. mi->bank[0].size = 114*1024*1024;
  203. #elif defined(CONFIG_RESERVED_MEM_JPEG_MFC_POST)
  204. mi->bank[0].size = 106*1024*1024;
  205. #elif defined(CONFIG_RESERVED_MEM_JPEG_CAMERA)
  206. mi->bank[0].size = 105*1024*1024;
  207. #elif defined(CONFIG_RESERVED_MEM_JPEG_POST_CAMERA)
  208. mi->bank[0].size = 97*1024*1024;
  209. #elif defined(CONFIG_RESERVED_MEM_MFC_CAMERA)
  210. mi->bank[0].size = 107*1024*1024;
  211. #elif defined(CONFIG_RESERVED_MEM_MFC_POST_CAMERA)
  212. mi->bank[0].size = 99*1024*1024;
  213. #elif defined(CONFIG_RESERVED_MEM_JPEG_MFC_POST_CAMERA)
  214. mi->bank[0].size = 91*1024*1024;
  215. #elif defined(CONFIG_RESERVED_MEM_CMM_MFC_POST)
  216. mi->bank[0].size = 106*1024*1024;
  217. #elif defined(CONFIG_RESERVED_MEM_CMM_JPEG_MFC_POST_CAMERA)
  218. mi->bank[0].size = 83*1024*1024;
  219. #elif defined(CONFIG_VIDEO_SAMSUNG)
  220. mi->bank[0].size = 113*1024*1024;
  221. #else
  222. mi->bank[0].size = 128*1024*1024;
  223. #endif
  224. mi->bank[0].node = 0;
  225. mi->nr_banks = 1;
  226. }
  227. void smdk6410_hsmmc_init (void)
  228. {
  229. /* hsmmc data strength */
  230. writel(readl(S3C_SPCON) | (0x3 << 26), S3C_SPCON);
  231. /* jsgood: hsmmc0/1 card detect pin should be high before setup gpio. (GPG6 to Input) */
  232. writel(readl(S3C_GPGCON) & 0xf0ffffff, S3C_GPGCON);
  233. /* GPIO N 13 (external interrupt) : Chip detect */
  234. s3c_gpio_cfgpin(S3C_GPN13, S3C_GPN13_EXTINT13); /* GPN13 to EINT13 */
  235. s3c_gpio_pullup(S3C_GPN13, 0x2); /* Pull-up Enable */
  236. /* jsgood: MUXmmc# to DOUTmpll for MPLL Clock Source */
  237. writel((readl(S3C_CLK_SRC) & ~(0x3f << 18)) | (0x15 << 18), S3C_CLK_SRC);
  238. #if defined(CONFIG_MACH_SANJOSE2)
  239. /* for hsmmc ch2 */
  240. writel(0, S3C_GPNPU);
  241. writel((readl(S3C_GPNCON) & ~(0x3 << 24)) | (0x2 << 24), S3C_GPNCON); /* GPN12 to EINT */
  242. writel(readl(S3C_EINT0CON0) | (0x3 << 25), S3C_EINT0CON0); /* EINT12 to both edge triggered */
  243. writel(readl(S3C_EINT0MASK) & ~(0x1 << 12), S3C_EINT0MASK); /* EINT12 unmask */
  244. writel(readl(S3C_VIC1INTENABLE) | (0x1 << 0), S3C_VIC1INTENABLE); /* EINT12 enable */
  245. #endif
  246. }
  247. #if 0 /* removed otg reset due to change mmc clock source USB clock to MPLL */
  248. static void smdk6410_usb_otg_reset (void)
  249. {
  250. #if defined(CONFIG_MACH_SANJOSE2)
  251. /* GPC7 to high for usb power up */
  252. s3c_gpio_cfgpin(S3C_GPC7, S3C_GPC7_OUTP);
  253. s3c_gpio_setpin(S3C_GPC7, 1);
  254. #endif
  255. /* initialize for usb 48m ext clock */
  256. writel(readl(S3C_OTHERS) | S3C_OTHERS_USB_SIG_MASK, S3C_OTHERS);
  257. writel(0x0, S3C_USBOTG_PHYPWR);
  258. writel(0x20, S3C_USBOTG_PHYCLK);
  259. writel(0x1, S3C_USBOTG_RSTCON);
  260. udelay(50);
  261. writel(0x0, S3C_USBOTG_RSTCON);
  262. udelay(50);
  263. }
  264. #endif
  265. static void __init smdk6410_machine_init (void)
  266. {
  267. smdk6410_cs89x0_set();
  268. smdk_machine_init();
  269. #if 0 /* removed otg reset due to change mmc clock source USB clock to MPLL */
  270. smdk6410_usb_otg_reset();
  271. #endif
  272. smdk6410_hsmmc_init();
  273. }
  274. MACHINE_START(SMDK6430, "SMDK6430")
  275. /* Maintainer: Samsung Electronics */
  276. .phys_io = S3C24XX_PA_UART,
  277. .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
  278. .boot_params = S3C_SDRAM_PA + 0x100,
  279. .init_irq = s3c_init_irq,
  280. .map_io = smdk6410_map_io,
  281. .fixup = smdk6410_fixup,
  282. .timer = &s3c_timer,
  283. .init_machine = smdk6410_machine_init,
  284. MACHINE_END
  285. /*--------------------------------------------------------------
  286. * HS-MMC GPIO Set function
  287. * the location of this function must be re-considered.
  288. * by scsuh
  289. *--------------------------------------------------------------*/
  290. void hsmmc_set_gpio (uint channel, uint width)
  291. {
  292. switch (channel) {
  293. /* can supports 1 and 4 bit bus */
  294. case 0:
  295. /* GPIO G : Command, Clock */
  296. s3c_gpio_cfgpin(S3C_GPG0, S3C_GPG0_MMC_CLK0);
  297. s3c_gpio_cfgpin(S3C_GPG1, S3C_GPG1_MMC_CMD0);
  298. s3c_gpio_pullup(S3C_GPG0, 0x0); /* Pull-up/down disable */
  299. s3c_gpio_pullup(S3C_GPG1, 0x0); /* Pull-up/down disable */
  300. /* GPIO G : Chip detect + LED */
  301. s3c_gpio_cfgpin(S3C_GPG6, S3C_GPG6_MMC_CD1);
  302. s3c_gpio_pullup(S3C_GPG6, 0x2); /* Pull-up Enable */
  303. if (width == 1) {
  304. /* GPIO G : MMC DATA1[0] */
  305. s3c_gpio_cfgpin(S3C_GPG2, S3C_GPG2_MMC_DATA0_0);
  306. s3c_gpio_pullup(S3C_GPG2, 0x0); /* Pull-up/down disable */
  307. }
  308. else if (width == 4) {
  309. /* GPIO G : MMC DATA1[0:3] */
  310. s3c_gpio_cfgpin(S3C_GPG2, S3C_GPG2_MMC_DATA0_0);
  311. s3c_gpio_cfgpin(S3C_GPG3, S3C_GPG3_MMC_DATA0_1);
  312. s3c_gpio_cfgpin(S3C_GPG4, S3C_GPG4_MMC_DATA0_2);
  313. s3c_gpio_cfgpin(S3C_GPG5, S3C_GPG5_MMC_DATA0_3);
  314. s3c_gpio_pullup(S3C_GPG2, 0x0); /* Pull-up/down disable */
  315. s3c_gpio_pullup(S3C_GPG3, 0x0); /* Pull-up/down disable */
  316. s3c_gpio_pullup(S3C_GPG4, 0x0); /* Pull-up/down disable */
  317. s3c_gpio_pullup(S3C_GPG5, 0x0); /* Pull-up/down disable */
  318. }
  319. break;
  320. /* can supports 1, 4, and 8 bit bus */
  321. case 1:
  322. /* GPIO H : Command, Clock */
  323. s3c_gpio_cfgpin(S3C_GPH0, S3C_GPH0_MMC_CLK1);
  324. s3c_gpio_cfgpin(S3C_GPH1, S3C_GPH1_MMC_CMD1);
  325. s3c_gpio_pullup(S3C_GPH0, 0x0); /* Pull-up/down disable */
  326. s3c_gpio_pullup(S3C_GPH1, 0x0); /* Pull-up/down disable */
  327. /* GPIO G : Chip detect + LED */
  328. s3c_gpio_cfgpin(S3C_GPG6, S3C_GPG6_MMC_CD1);
  329. s3c_gpio_pullup(S3C_GPG6, 0x2); /* Pull-up Enable */
  330. if (width == 1) {
  331. /* GPIO H : MMC DATA1[0] */
  332. s3c_gpio_cfgpin(S3C_GPH2, S3C_GPH2_MMC_DATA1_0);
  333. s3c_gpio_pullup(S3C_GPH2, 0x0); /* Pull-up/down disable */
  334. }
  335. else if (width == 4) {
  336. /* GPIO H : MMC DATA1[0:3] */
  337. s3c_gpio_cfgpin(S3C_GPH2, S3C_GPH2_MMC_DATA1_0);
  338. s3c_gpio_cfgpin(S3C_GPH3, S3C_GPH3_MMC_DATA1_1);
  339. s3c_gpio_cfgpin(S3C_GPH4, S3C_GPH4_MMC_DATA1_2);
  340. s3c_gpio_cfgpin(S3C_GPH5, S3C_GPH5_MMC_DATA1_3);
  341. s3c_gpio_pullup(S3C_GPH2, 0x0); /* Pull-up/down disable */
  342. s3c_gpio_pullup(S3C_GPH3, 0x0); /* Pull-up/down disable */
  343. s3c_gpio_pullup(S3C_GPH4, 0x0); /* Pull-up/down disable */
  344. s3c_gpio_pullup(S3C_GPH5, 0x0); /* Pull-up/down disable */
  345. }
  346. else if (width == 8) {
  347. /* GPIO H : MMC DATA1[0:7] */
  348. s3c_gpio_cfgpin(S3C_GPH2, S3C_GPH2_MMC_DATA1_0);
  349. s3c_gpio_cfgpin(S3C_GPH3, S3C_GPH3_MMC_DATA1_1);
  350. s3c_gpio_cfgpin(S3C_GPH4, S3C_GPH4_MMC_DATA1_2);
  351. s3c_gpio_cfgpin(S3C_GPH5, S3C_GPH5_MMC_DATA1_3);
  352. s3c_gpio_cfgpin(S3C_GPH6, S3C_GPH6_MMC_DATA1_4);
  353. s3c_gpio_cfgpin(S3C_GPH7, S3C_GPH7_MMC_DATA1_5);
  354. s3c_gpio_cfgpin(S3C_GPH8, S3C_GPH8_MMC_DATA1_6);
  355. s3c_gpio_cfgpin(S3C_GPH9, S3C_GPH9_MMC_DATA1_7);
  356. s3c_gpio_pullup(S3C_GPH2, 0x0); /* Pull-up/down disable */
  357. s3c_gpio_pullup(S3C_GPH3, 0x0); /* Pull-up/down disable */
  358. s3c_gpio_pullup(S3C_GPH4, 0x0); /* Pull-up/down disable */
  359. s3c_gpio_pullup(S3C_GPH5, 0x0); /* Pull-up/down disable */
  360. s3c_gpio_pullup(S3C_GPH6, 0x0); /* Pull-up/down disable */
  361. s3c_gpio_pullup(S3C_GPH7, 0x0); /* Pull-up/down disable */
  362. s3c_gpio_pullup(S3C_GPH8, 0x0); /* Pull-up/down disable */
  363. s3c_gpio_pullup(S3C_GPH9, 0x0); /* Pull-up/down disable */
  364. }
  365. break;
  366. /* can supports 1 and 4 bit bus, no irq_cd */
  367. case 2:
  368. /* GPIO H : Command, Clock */
  369. s3c_gpio_cfgpin(S3C_GPH0, S3C_GPH0_MMC_CLK1);
  370. s3c_gpio_cfgpin(S3C_GPH1, S3C_GPH1_MMC_CMD1);
  371. s3c_gpio_pullup(S3C_GPH0, 0x0); /* Pull-up/down disable */
  372. s3c_gpio_pullup(S3C_GPH1, 0x0); /* Pull-up/down disable */
  373. /* GPIO G : Chip detect + LED */
  374. s3c_gpio_cfgpin(S3C_GPG6, S3C_GPG6_MMC_CD1);
  375. s3c_gpio_pullup(S3C_GPG6, 0x2); /* Pull-up Enable */
  376. if (width == 1) {
  377. /* GPIO H : MMC DATA1[0] */
  378. s3c_gpio_cfgpin(S3C_GPH6, S3C_GPH6_MMC_DATA2_0);
  379. s3c_gpio_pullup(S3C_GPH6, 0x0); /* Pull-up/down disable */
  380. }
  381. else if (width == 4) {
  382. /* GPIO H : MMC DATA1[0:3] */
  383. s3c_gpio_cfgpin(S3C_GPH6, S3C_GPH6_MMC_DATA2_0);
  384. s3c_gpio_cfgpin(S3C_GPH7, S3C_GPH7_MMC_DATA2_1);
  385. s3c_gpio_cfgpin(S3C_GPH8, S3C_GPH8_MMC_DATA2_2);
  386. s3c_gpio_cfgpin(S3C_GPH9, S3C_GPH9_MMC_DATA2_3);
  387. s3c_gpio_pullup(S3C_GPH6, 0x0); /* Pull-up/down disable */
  388. s3c_gpio_pullup(S3C_GPH7, 0x0); /* Pull-up/down disable */
  389. s3c_gpio_pullup(S3C_GPH8, 0x0); /* Pull-up/down disable */
  390. s3c_gpio_pullup(S3C_GPH9, 0x0); /* Pull-up/down disable */
  391. }
  392. break;
  393. default:
  394. break;
  395. }
  396. }
  397. /* For host controller's capabilities */
  398. #define HOST_CAPS (MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | \
  399. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)
  400. struct s3c_hsmmc_cfg s3c_hsmmc0_platform = {
  401. .hwport = 0,
  402. .enabled = 0,
  403. .host_caps = HOST_CAPS,
  404. .bus_width = 4,
  405. .highspeed = 0,
  406. /* ctrl for mmc */
  407. .fd_ctrl[MMC_MODE_MMC] = {
  408. .ctrl2 = 0xC0004100, /* ctrl2 for mmc */
  409. .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
  410. .ctrl3[SPEED_HIGH] = 0x00000080, /* ctrl3 for high speed */
  411. .ctrl4 = 0x3,
  412. },
  413. /* ctrl for sd */
  414. .fd_ctrl[MMC_MODE_SD] = {
  415. .ctrl2 = 0xC0004100, /* ctrl2 for sd */
  416. .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
  417. .ctrl3[SPEED_HIGH] = 0x00000080, /* ctrl3 for high speed */
  418. .ctrl4 = 0x3,
  419. },
  420. /*
  421. * Warning: Do not change the order of clk_name[]
  422. * The index number + 1 is used to value for SELBASECLK in CONTROL2 register for Base Clock Source Select
  423. */
  424. .clk_name[0] = "",
  425. .clk_name[1] = "sclk_DOUTmpll_mmc0",
  426. };
  427. struct s3c_hsmmc_cfg s3c_hsmmc1_platform = {
  428. .hwport = 1,
  429. .enabled = 1,
  430. .host_caps = HOST_CAPS,
  431. .bus_width = 4,
  432. .highspeed = 0,
  433. /* ctrl for mmc */
  434. .fd_ctrl[MMC_MODE_MMC] = {
  435. .ctrl2 = 0xC0004100, /* ctrl2 for mmc */
  436. .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
  437. .ctrl3[SPEED_HIGH] = 0x00000080, /* ctrl3 for high speed */
  438. .ctrl4 = 0x3,
  439. },
  440. /* ctrl for sd */
  441. .fd_ctrl[MMC_MODE_SD] = {
  442. .ctrl2 = 0xC0004100, /* ctrl2 for sd */
  443. .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
  444. .ctrl3[SPEED_HIGH] = 0x00000080, /* ctrl3 for high speed */
  445. .ctrl4 = 0x3,
  446. },
  447. /*
  448. * Warning: Do not change the order of clk_name[]
  449. * The index number + 1 is used to value for SELBASECLK in CONTROL2 register for Base Clock Source Select
  450. */
  451. .clk_name[0] = "",
  452. .clk_name[1] = "sclk_DOUTmpll_mmc1",
  453. };
  454. struct s3c_hsmmc_cfg s3c_hsmmc2_platform = {
  455. .hwport = 2,
  456. .enabled = 0,
  457. .host_caps = HOST_CAPS,
  458. .bus_width = 4,
  459. .highspeed = 0,
  460. /* ctrl for mmc */
  461. .fd_ctrl[MMC_MODE_MMC] = {
  462. .ctrl2 = 0xC0004100, /* ctrl2 for mmc */
  463. .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
  464. .ctrl3[SPEED_HIGH] = 0x00000080, /* ctrl3 for high speed */
  465. .ctrl4 = 0x3,
  466. },
  467. /* ctrl for sd */
  468. .fd_ctrl[MMC_MODE_SD] = {
  469. .ctrl2 = 0xC0004100, /* ctrl2 for sd */
  470. .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
  471. .ctrl3[SPEED_HIGH] = 0x00000080, /* ctrl3 for high speed */
  472. .ctrl4 = 0x3,
  473. },
  474. /*
  475. * Warning: Do not change the order of clk_name[]
  476. * The index number + 1 is used to value for SELBASECLK in CONTROL2 register for Base Clock Source Select
  477. */
  478. .clk_name[0] = "",
  479. .clk_name[1] = "sclk_DOUTmpll_mmc2",
  480. };