dma.c 6.6 KB

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  1. /* linux/arch/arm/mach-s3c6400/dma.c
  2. *
  3. * Copyright (c) 2003-2005,2006 Samsung Electronics
  4. *
  5. * S3C6400 DMA selection
  6. *
  7. * http://www.samsung.com/
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/sysdev.h>
  16. #include <linux/serial_core.h>
  17. #include <asm/dma.h>
  18. #include <asm/arch/dma.h>
  19. #include <asm/io.h>
  20. #include <asm/plat-s3c24xx/dma.h>
  21. #include <asm/plat-s3c24xx/cpu.h>
  22. /* DMAC-0 */
  23. #define MAP0(x) { \
  24. [0] = (x) | DMA_CH_VALID, \
  25. [1] = (x) | DMA_CH_VALID, \
  26. [2] = (x) | DMA_CH_VALID, \
  27. [3] = (x) | DMA_CH_VALID, \
  28. [4] = (x) | DMA_CH_VALID, \
  29. [5] = (x) | DMA_CH_VALID, \
  30. [6] = (x) | DMA_CH_VALID, \
  31. [7] = (x) | DMA_CH_VALID, \
  32. [8] = (x), \
  33. [9] = (x), \
  34. [10] = (x), \
  35. [11] = (x), \
  36. [12] = (x), \
  37. [13] = (x), \
  38. [14] = (x), \
  39. [15] = (x), \
  40. [16] = (x), \
  41. [17] = (x), \
  42. [18] = (x), \
  43. [19] = (x), \
  44. [20] = (x), \
  45. [21] = (x), \
  46. [22] = (x), \
  47. [23] = (x), \
  48. [24] = (x), \
  49. [25] = (x), \
  50. [26] = (x), \
  51. [27] = (x), \
  52. [28] = (x), \
  53. [29] = (x), \
  54. [30] = (x), \
  55. [31] = (x), \
  56. }
  57. /* DMAC-1 */
  58. #define MAP1(x) { \
  59. [0] = (x), \
  60. [1] = (x), \
  61. [2] = (x), \
  62. [3] = (x), \
  63. [4] = (x), \
  64. [5] = (x), \
  65. [6] = (x), \
  66. [7] = (x), \
  67. [8] = (x) | DMA_CH_VALID, \
  68. [9] = (x) | DMA_CH_VALID, \
  69. [10] = (x) | DMA_CH_VALID, \
  70. [11] = (x) | DMA_CH_VALID, \
  71. [12] = (x) | DMA_CH_VALID, \
  72. [13] = (x) | DMA_CH_VALID, \
  73. [14] = (x) | DMA_CH_VALID, \
  74. [15] = (x) | DMA_CH_VALID, \
  75. [16] = (x), \
  76. [17] = (x), \
  77. [18] = (x), \
  78. [19] = (x), \
  79. [20] = (x), \
  80. [21] = (x), \
  81. [22] = (x), \
  82. [23] = (x), \
  83. [24] = (x), \
  84. [25] = (x), \
  85. [26] = (x), \
  86. [27] = (x), \
  87. [28] = (x), \
  88. [29] = (x), \
  89. [30] = (x), \
  90. [31] = (x), \
  91. }
  92. /* SDMAC-0 */
  93. #define MAP2(x) { \
  94. [0] = (x), \
  95. [1] = (x), \
  96. [2] = (x), \
  97. [3] = (x), \
  98. [4] = (x), \
  99. [5] = (x), \
  100. [6] = (x), \
  101. [7] = (x), \
  102. [8] = (x), \
  103. [9] = (x), \
  104. [10] = (x), \
  105. [11] = (x), \
  106. [12] = (x), \
  107. [13] = (x), \
  108. [14] = (x), \
  109. [15] = (x), \
  110. [16] = (x) | DMA_CH_VALID, \
  111. [17] = (x) | DMA_CH_VALID, \
  112. [18] = (x) | DMA_CH_VALID, \
  113. [19] = (x) | DMA_CH_VALID, \
  114. [20] = (x) | DMA_CH_VALID, \
  115. [21] = (x) | DMA_CH_VALID, \
  116. [22] = (x) | DMA_CH_VALID, \
  117. [23] = (x) | DMA_CH_VALID, \
  118. [24] = (x), \
  119. [25] = (x), \
  120. [26] = (x), \
  121. [27] = (x), \
  122. [28] = (x), \
  123. [29] = (x), \
  124. [30] = (x), \
  125. [31] = (x), \
  126. }
  127. /* SDMAC-1 */
  128. #define MAP3(x) { \
  129. [0] = (x), \
  130. [1] = (x), \
  131. [2] = (x), \
  132. [3] = (x), \
  133. [4] = (x), \
  134. [5] = (x), \
  135. [6] = (x), \
  136. [7] = (x), \
  137. [8] = (x), \
  138. [9] = (x), \
  139. [10] = (x), \
  140. [11] = (x), \
  141. [12] = (x), \
  142. [13] = (x), \
  143. [14] = (x), \
  144. [15] = (x), \
  145. [16] = (x), \
  146. [17] = (x), \
  147. [18] = (x), \
  148. [19] = (x), \
  149. [20] = (x), \
  150. [21] = (x), \
  151. [22] = (x), \
  152. [23] = (x), \
  153. [24] = (x) | DMA_CH_VALID, \
  154. [25] = (x) | DMA_CH_VALID, \
  155. [26] = (x) | DMA_CH_VALID, \
  156. [27] = (x) | DMA_CH_VALID, \
  157. [28] = (x) | DMA_CH_VALID, \
  158. [29] = (x) | DMA_CH_VALID, \
  159. [30] = (x) | DMA_CH_VALID, \
  160. [31] = (x) | DMA_CH_VALID, \
  161. }
  162. /* SDMAC-0 */
  163. #define MAP2_ONENAND(x) { \
  164. [0] = (x), \
  165. [1] = (x), \
  166. [2] = (x), \
  167. [3] = (x) , \
  168. [4] = (x), \
  169. [5] = (x), \
  170. [6] = (x), \
  171. [7] = (x), \
  172. [8] = (x), \
  173. [9] = (x), \
  174. [10] = (x), \
  175. [11] = (x), \
  176. [12] = (x), \
  177. [13] = (x), \
  178. [14] = (x), \
  179. [15] = (x), \
  180. [16] = (x), \
  181. [17] = (x), \
  182. [18] = (x) , \
  183. [19] = (x) | DMA_CH_VALID, \
  184. [20] = (x), \
  185. [21] = (x), \
  186. [22] = (x), \
  187. [23] = (x), \
  188. [24] = (x), \
  189. [25] = (x), \
  190. [26] = (x), \
  191. [27] = (x), \
  192. [28] = (x), \
  193. [29] = (x), \
  194. [30] = (x), \
  195. [31] = (x), \
  196. }
  197. static struct s3c24xx_dma_map __initdata s3c6400_dma_mappings[] = {
  198. [DMACH_I2S_IN] = {
  199. .name = "i2s0-in",
  200. .channels = MAP0(S3C_DMA0_I2S0_RX),
  201. .hw_addr.from = S3C_DMA0_I2S0_RX,
  202. .sdma_sel = 1 << S3C_DMA0_I2S0_RX,
  203. },
  204. [DMACH_I2S_OUT] = {
  205. .name = "i2s0-out",
  206. .channels = MAP0(S3C_DMA0_I2S0_TX),
  207. .hw_addr.to = S3C_DMA0_I2S0_TX,
  208. .sdma_sel = 1 << S3C_DMA0_I2S0_TX,
  209. /* Using for Full duplex */
  210. //.sdma_sel = 1 << (S3C_DMA0_I2S0_TX + S3C_DMA2),
  211. },
  212. [DMACH_I2S1_IN] = {
  213. .name = "i2s1-in",
  214. .channels = MAP1(S3C_DMA1_I2S1_RX),
  215. .hw_addr.from = S3C_DMA1_I2S1_RX,
  216. .sdma_sel = 1 << (S3C_DMA1_I2S1_RX+S3C_DMA1),
  217. },
  218. [DMACH_I2S1_OUT] = {
  219. .name = "i2s1-out",
  220. .channels = MAP1(S3C_DMA1_I2S1_TX),
  221. .hw_addr.to = S3C_DMA1_I2S1_TX,
  222. .sdma_sel = 1 << (S3C_DMA1_I2S1_TX+S3C_DMA1),
  223. },
  224. [DMACH_SPI0_IN] = {
  225. .name = "spi0-in",
  226. .channels = MAP0(S3C_DMA0_SPI0_RX),
  227. .hw_addr.from = S3C_DMA0_SPI0_RX,
  228. .sdma_sel = 1 << S3C_DMA0_SPI0_RX,
  229. },
  230. [DMACH_SPI0_OUT] = {
  231. .name = "spi0-out",
  232. .channels = MAP0(S3C_DMA0_SPI0_TX),
  233. .hw_addr.to = S3C_DMA0_SPI0_TX,
  234. .sdma_sel = 1 << S3C_DMA0_SPI0_TX,
  235. },
  236. [DMACH_SPI1_IN] = {
  237. .name = "spi1-in",
  238. .channels = MAP1(S3C_DMA1_SPI1_RX),
  239. .hw_addr.from = S3C_DMA1_SPI1_RX,
  240. .sdma_sel = 1 << (S3C_DMA1_SPI1_RX+S3C_DMA1),
  241. },
  242. [DMACH_SPI1_OUT] = {
  243. .name = "spi1-out",
  244. .channels = MAP1(S3C_DMA1_SPI1_TX),
  245. .hw_addr.to = S3C_DMA1_SPI1_TX,
  246. .sdma_sel = 1 << (S3C_DMA1_SPI1_TX+S3C_DMA1),
  247. },
  248. [DMACH_AC97_PCM_OUT] = {
  249. .name = "ac97-pcm-out",
  250. .channels = MAP3(S3C_DMA1_AC97_PCMOUT),
  251. .hw_addr.to = S3C_DMA1_AC97_PCMOUT,
  252. .sdma_sel = 1 << (S3C_DMA1_AC97_PCMOUT),
  253. },
  254. [DMACH_AC97_PCM_IN] = {
  255. .name = "ac97-pcm-in",
  256. .channels = MAP1(S3C_DMA1_AC97_PCMIN),
  257. .hw_addr.from = S3C_DMA1_AC97_PCMIN,
  258. .sdma_sel = 1 << (S3C_DMA1_AC97_PCMIN+S3C_DMA1),
  259. },
  260. [DMACH_AC97_MIC_IN] = {
  261. .name = "ac97-mic-in",
  262. .channels = MAP1(S3C_DMA1_AC97_MICIN),
  263. .hw_addr.from = S3C_DMA1_AC97_MICIN,
  264. .sdma_sel = 1 << (S3C_DMA1_AC97_MICIN+S3C_DMA1),
  265. },
  266. [DMACH_ONENAND_IN] = {
  267. .name = "onenand-in",
  268. .channels = MAP2_ONENAND(S3C_DMA0_ONENAND_RX),
  269. .hw_addr.from = S3C_DMA0_ONENAND_RX,
  270. },
  271. };
  272. static void s3c6400_dma_select(struct s3c2410_dma_chan *chan,
  273. struct s3c24xx_dma_map *map)
  274. {
  275. chan->map = map;
  276. }
  277. static struct s3c24xx_dma_selection __initdata s3c6400_dma_sel = {
  278. .select = s3c6400_dma_select,
  279. .dcon_mask = 0,
  280. .map = s3c6400_dma_mappings,
  281. .map_size = ARRAY_SIZE(s3c6400_dma_mappings),
  282. };
  283. static int s3c6400_dma_add(struct sys_device *sysdev)
  284. {
  285. s3c24xx_dma_init(S3C2410_DMA_CHANNELS, IRQ_DMA0, 0x20);
  286. return s3c24xx_dma_init_map(&s3c6400_dma_sel);
  287. }
  288. static struct sysdev_driver s3c6400_dma_driver = {
  289. .add = s3c6400_dma_add,
  290. };
  291. static int __init s3c6400_dma_init(void)
  292. {
  293. return sysdev_driver_register(&s3c6400_sysclass, &s3c6400_dma_driver);
  294. }
  295. arch_initcall(s3c6400_dma_init);