clock.c 4.2 KB

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  1. /* linux/arch/arm/mach-s3c2442/clock.c
  2. *
  3. * Copyright (c) 2004-2005 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * S3C2442 Clock support
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #include <linux/init.h>
  24. #include <linux/module.h>
  25. #include <linux/kernel.h>
  26. #include <linux/list.h>
  27. #include <linux/errno.h>
  28. #include <linux/err.h>
  29. #include <linux/device.h>
  30. #include <linux/sysdev.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/ioport.h>
  33. #include <linux/mutex.h>
  34. #include <linux/clk.h>
  35. #include <asm/hardware.h>
  36. #include <asm/atomic.h>
  37. #include <asm/irq.h>
  38. #include <asm/io.h>
  39. #include <asm/arch/regs-clock.h>
  40. #include <asm/plat-s3c24xx/clock.h>
  41. #include <asm/plat-s3c24xx/cpu.h>
  42. /* S3C2442 extended clock support */
  43. static unsigned long s3c2442_camif_upll_round(struct clk *clk,
  44. unsigned long rate)
  45. {
  46. unsigned long parent_rate = clk_get_rate(clk->parent);
  47. int div;
  48. if (rate > parent_rate)
  49. return parent_rate;
  50. div = parent_rate / rate;
  51. if (div == 3)
  52. return parent_rate / 3;
  53. /* note, we remove the +/- 1 calculations for the divisor */
  54. div /= 2;
  55. if (div < 1)
  56. div = 1;
  57. else if (div > 16)
  58. div = 16;
  59. return parent_rate / (div * 2);
  60. }
  61. static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
  62. {
  63. unsigned long parent_rate = clk_get_rate(clk->parent);
  64. unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
  65. rate = s3c2442_camif_upll_round(clk, rate);
  66. camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
  67. if (rate == parent_rate) {
  68. camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
  69. } else if ((parent_rate / rate) == 3) {
  70. camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
  71. camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
  72. } else {
  73. camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
  74. camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
  75. camdivn |= (((parent_rate / rate) / 2) - 1);
  76. }
  77. __raw_writel(camdivn, S3C2440_CAMDIVN);
  78. return 0;
  79. }
  80. /* Extra S3C2442 clocks */
  81. static struct clk s3c2442_clk_cam = {
  82. .name = "camif",
  83. .id = -1,
  84. .enable = s3c2410_clkcon_enable,
  85. .ctrlbit = S3C2440_CLKCON_CAMERA,
  86. };
  87. static struct clk s3c2442_clk_cam_upll = {
  88. .name = "camif-upll",
  89. .id = -1,
  90. .set_rate = s3c2442_camif_upll_setrate,
  91. .round_rate = s3c2442_camif_upll_round,
  92. };
  93. static int s3c2442_clk_add(struct sys_device *sysdev)
  94. {
  95. unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
  96. unsigned long clkdivn;
  97. struct clk *clock_h;
  98. struct clk *clock_p;
  99. struct clk *clock_upll;
  100. printk("S3C2442: Clock Support, DVS %s\n",
  101. (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
  102. clock_p = clk_get(NULL, "pclk");
  103. clock_h = clk_get(NULL, "hclk");
  104. clock_upll = clk_get(NULL, "upll");
  105. if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
  106. printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
  107. return -EINVAL;
  108. }
  109. /* check rate of UPLL, and if it is near 96MHz, then change
  110. * to using half the UPLL rate for the system */
  111. if (clk_get_rate(clock_upll) > (94 * MHZ)) {
  112. clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
  113. mutex_lock(&clocks_mutex);
  114. clkdivn = __raw_readl(S3C2410_CLKDIVN);
  115. clkdivn |= S3C2440_CLKDIVN_UCLK;
  116. __raw_writel(clkdivn, S3C2410_CLKDIVN);
  117. mutex_unlock(&clocks_mutex);
  118. }
  119. s3c2442_clk_cam.parent = clock_h;
  120. s3c2442_clk_cam_upll.parent = clock_upll;
  121. s3c24xx_register_clock(&s3c2442_clk_cam);
  122. s3c24xx_register_clock(&s3c2442_clk_cam_upll);
  123. clk_disable(&s3c2442_clk_cam);
  124. return 0;
  125. }
  126. static struct sysdev_driver s3c2442_clk_driver = {
  127. .add = s3c2442_clk_add,
  128. };
  129. static __init int s3c2442_clk_init(void)
  130. {
  131. return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
  132. }
  133. arch_initcall(s3c2442_clk_init);