mach-osiris.c 6.9 KB

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  1. /* linux/arch/arm/mach-s3c2440/mach-osiris.c
  2. *
  3. * Copyright (c) 2005 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/types.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/list.h>
  15. #include <linux/timer.h>
  16. #include <linux/init.h>
  17. #include <linux/device.h>
  18. #include <linux/serial_core.h>
  19. #include <asm/mach/arch.h>
  20. #include <asm/mach/map.h>
  21. #include <asm/mach/irq.h>
  22. #include <asm/arch/osiris-map.h>
  23. #include <asm/arch/osiris-cpld.h>
  24. #include <asm/hardware.h>
  25. #include <asm/io.h>
  26. #include <asm/irq.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/arch/regs-serial.h>
  29. #include <asm/arch/regs-gpio.h>
  30. #include <asm/arch/regs-mem.h>
  31. #include <asm/arch/regs-lcd.h>
  32. #include <asm/arch/nand.h>
  33. #include <linux/mtd/mtd.h>
  34. #include <linux/mtd/nand.h>
  35. #include <linux/mtd/nand_ecc.h>
  36. #include <linux/mtd/partitions.h>
  37. #include <asm/plat-s3c24xx/clock.h>
  38. #include <asm/plat-s3c24xx/devs.h>
  39. #include <asm/plat-s3c24xx/cpu.h>
  40. /* onboard perihpheral map */
  41. static struct map_desc osiris_iodesc[] __initdata = {
  42. /* ISA IO areas (may be over-written later) */
  43. {
  44. .virtual = (u32)S3C24XX_VA_ISA_BYTE,
  45. .pfn = __phys_to_pfn(S3C2410_CS5),
  46. .length = SZ_16M,
  47. .type = MT_DEVICE,
  48. }, {
  49. .virtual = (u32)S3C24XX_VA_ISA_WORD,
  50. .pfn = __phys_to_pfn(S3C2410_CS5),
  51. .length = SZ_16M,
  52. .type = MT_DEVICE,
  53. },
  54. /* CPLD control registers */
  55. {
  56. .virtual = (u32)OSIRIS_VA_CTRL1,
  57. .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
  58. .length = SZ_16K,
  59. .type = MT_DEVICE,
  60. }, {
  61. .virtual = (u32)OSIRIS_VA_CTRL2,
  62. .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
  63. .length = SZ_16K,
  64. .type = MT_DEVICE,
  65. },
  66. };
  67. #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  68. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  69. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  70. static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
  71. [0] = {
  72. .name = "uclk",
  73. .divisor = 1,
  74. .min_baud = 0,
  75. .max_baud = 0,
  76. },
  77. [1] = {
  78. .name = "pclk",
  79. .divisor = 1,
  80. .min_baud = 0,
  81. .max_baud = 0,
  82. }
  83. };
  84. static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
  85. [0] = {
  86. .hwport = 0,
  87. .flags = 0,
  88. .ucon = UCON,
  89. .ulcon = ULCON,
  90. .ufcon = UFCON,
  91. .clocks = osiris_serial_clocks,
  92. .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
  93. },
  94. [1] = {
  95. .hwport = 1,
  96. .flags = 0,
  97. .ucon = UCON,
  98. .ulcon = ULCON,
  99. .ufcon = UFCON,
  100. .clocks = osiris_serial_clocks,
  101. .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
  102. },
  103. [2] = {
  104. .hwport = 2,
  105. .flags = 0,
  106. .ucon = UCON,
  107. .ulcon = ULCON,
  108. .ufcon = UFCON,
  109. .clocks = osiris_serial_clocks,
  110. .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
  111. }
  112. };
  113. /* NAND Flash on Osiris board */
  114. static int external_map[] = { 2 };
  115. static int chip0_map[] = { 0 };
  116. static int chip1_map[] = { 1 };
  117. static struct mtd_partition osiris_default_nand_part[] = {
  118. [0] = {
  119. .name = "Boot Agent",
  120. .size = SZ_16K,
  121. .offset = 0,
  122. },
  123. [1] = {
  124. .name = "/boot",
  125. .size = SZ_4M - SZ_16K,
  126. .offset = SZ_16K,
  127. },
  128. [2] = {
  129. .name = "user1",
  130. .offset = SZ_4M,
  131. .size = SZ_32M - SZ_4M,
  132. },
  133. [3] = {
  134. .name = "user2",
  135. .offset = SZ_32M,
  136. .size = MTDPART_SIZ_FULL,
  137. }
  138. };
  139. /* the Osiris has 3 selectable slots for nand-flash, the two
  140. * on-board chip areas, as well as the external slot.
  141. *
  142. * Note, there is no current hot-plug support for the External
  143. * socket.
  144. */
  145. static struct s3c2410_nand_set osiris_nand_sets[] = {
  146. [1] = {
  147. .name = "External",
  148. .nr_chips = 1,
  149. .nr_map = external_map,
  150. .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
  151. .partitions = osiris_default_nand_part,
  152. },
  153. [0] = {
  154. .name = "chip0",
  155. .nr_chips = 1,
  156. .nr_map = chip0_map,
  157. .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
  158. .partitions = osiris_default_nand_part,
  159. },
  160. [2] = {
  161. .name = "chip1",
  162. .nr_chips = 1,
  163. .nr_map = chip1_map,
  164. .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
  165. .partitions = osiris_default_nand_part,
  166. },
  167. };
  168. static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
  169. {
  170. unsigned int tmp;
  171. slot = set->nr_map[slot] & 3;
  172. pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
  173. slot, set, set->nr_map);
  174. tmp = __raw_readb(OSIRIS_VA_CTRL1);
  175. tmp &= ~OSIRIS_CTRL1_NANDSEL;
  176. tmp |= slot;
  177. pr_debug("osiris_nand: ctrl1 now %02x\n", tmp);
  178. __raw_writeb(tmp, OSIRIS_VA_CTRL1);
  179. }
  180. static struct s3c2410_platform_nand osiris_nand_info = {
  181. .tacls = 25,
  182. .twrph0 = 60,
  183. .twrph1 = 60,
  184. .nr_sets = ARRAY_SIZE(osiris_nand_sets),
  185. .sets = osiris_nand_sets,
  186. .select_chip = osiris_nand_select,
  187. };
  188. /* PCMCIA control and configuration */
  189. static struct resource osiris_pcmcia_resource[] = {
  190. [0] = {
  191. .start = 0x0f000000,
  192. .end = 0x0f100000,
  193. .flags = IORESOURCE_MEM,
  194. },
  195. [1] = {
  196. .start = 0x0c000000,
  197. .end = 0x0c100000,
  198. .flags = IORESOURCE_MEM,
  199. }
  200. };
  201. static struct platform_device osiris_pcmcia = {
  202. .name = "osiris-pcmcia",
  203. .id = -1,
  204. .num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
  205. .resource = osiris_pcmcia_resource,
  206. };
  207. /* Standard Osiris devices */
  208. static struct platform_device *osiris_devices[] __initdata = {
  209. &s3c_device_i2c,
  210. &s3c_device_nand,
  211. &osiris_pcmcia,
  212. };
  213. static struct clk *osiris_clocks[] = {
  214. &s3c24xx_dclk0,
  215. &s3c24xx_dclk1,
  216. &s3c24xx_clkout0,
  217. &s3c24xx_clkout1,
  218. &s3c24xx_uclk,
  219. };
  220. static struct s3c24xx_board osiris_board __initdata = {
  221. .devices = osiris_devices,
  222. .devices_count = ARRAY_SIZE(osiris_devices),
  223. .clocks = osiris_clocks,
  224. .clocks_count = ARRAY_SIZE(osiris_clocks),
  225. };
  226. static void __init osiris_map_io(void)
  227. {
  228. unsigned long flags;
  229. /* initialise the clocks */
  230. s3c24xx_dclk0.parent = NULL;
  231. s3c24xx_dclk0.rate = 12*1000*1000;
  232. s3c24xx_dclk1.parent = NULL;
  233. s3c24xx_dclk1.rate = 24*1000*1000;
  234. s3c24xx_clkout0.parent = &s3c24xx_dclk0;
  235. s3c24xx_clkout1.parent = &s3c24xx_dclk1;
  236. s3c24xx_uclk.parent = &s3c24xx_clkout1;
  237. s3c_device_nand.dev.platform_data = &osiris_nand_info;
  238. s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
  239. s3c24xx_init_clocks(0);
  240. s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
  241. s3c24xx_set_board(&osiris_board);
  242. /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
  243. local_irq_save(flags);
  244. __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
  245. local_irq_restore(flags);
  246. /* write-protect line to the NAND */
  247. s3c2410_gpio_setpin(S3C2410_GPA0, 1);
  248. }
  249. MACHINE_START(OSIRIS, "Simtec-OSIRIS")
  250. /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
  251. .phys_io = S3C2410_PA_UART,
  252. .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
  253. .boot_params = S3C2410_SDRAM_PA + 0x100,
  254. .map_io = osiris_map_io,
  255. .init_irq = s3c24xx_init_irq,
  256. .timer = &s3c24xx_timer,
  257. MACHINE_END