mach-anubis.c 7.3 KB

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  1. /* linux/arch/arm/mach-s3c2440/mach-anubis.c
  2. *
  3. * Copyright (c) 2003-2005 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/types.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/list.h>
  15. #include <linux/timer.h>
  16. #include <linux/init.h>
  17. #include <linux/serial_core.h>
  18. #include <linux/platform_device.h>
  19. #include <asm/mach/arch.h>
  20. #include <asm/mach/map.h>
  21. #include <asm/mach/irq.h>
  22. #include <asm/arch/anubis-map.h>
  23. #include <asm/arch/anubis-irq.h>
  24. #include <asm/arch/anubis-cpld.h>
  25. #include <asm/hardware.h>
  26. #include <asm/io.h>
  27. #include <asm/irq.h>
  28. #include <asm/mach-types.h>
  29. #include <asm/arch/regs-serial.h>
  30. #include <asm/arch/regs-gpio.h>
  31. #include <asm/arch/regs-mem.h>
  32. #include <asm/arch/regs-lcd.h>
  33. #include <asm/arch/nand.h>
  34. #include <linux/mtd/mtd.h>
  35. #include <linux/mtd/nand.h>
  36. #include <linux/mtd/nand_ecc.h>
  37. #include <linux/mtd/partitions.h>
  38. #include <asm/plat-s3c24xx/clock.h>
  39. #include <asm/plat-s3c24xx/devs.h>
  40. #include <asm/plat-s3c24xx/cpu.h>
  41. #define COPYRIGHT ", (c) 2005 Simtec Electronics"
  42. static struct map_desc anubis_iodesc[] __initdata = {
  43. /* ISA IO areas */
  44. {
  45. .virtual = (u32)S3C24XX_VA_ISA_BYTE,
  46. .pfn = __phys_to_pfn(0x0),
  47. .length = SZ_4M,
  48. .type = MT_DEVICE,
  49. }, {
  50. .virtual = (u32)S3C24XX_VA_ISA_WORD,
  51. .pfn = __phys_to_pfn(0x0),
  52. .length = SZ_4M,
  53. .type = MT_DEVICE,
  54. },
  55. /* we could possibly compress the next set down into a set of smaller tables
  56. * pagetables, but that would mean using an L2 section, and it still means
  57. * we cannot actually feed the same register to an LDR due to 16K spacing
  58. */
  59. /* CPLD control registers */
  60. {
  61. .virtual = (u32)ANUBIS_VA_CTRL1,
  62. .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
  63. .length = SZ_4K,
  64. .type = MT_DEVICE,
  65. }, {
  66. .virtual = (u32)ANUBIS_VA_CTRL2,
  67. .pfn = __phys_to_pfn(ANUBIS_PA_CTRL2),
  68. .length = SZ_4K,
  69. .type = MT_DEVICE,
  70. },
  71. };
  72. #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  73. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  74. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  75. static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
  76. [0] = {
  77. .name = "uclk",
  78. .divisor = 1,
  79. .min_baud = 0,
  80. .max_baud = 0,
  81. },
  82. [1] = {
  83. .name = "pclk",
  84. .divisor = 1,
  85. .min_baud = 0,
  86. .max_baud = 0,
  87. }
  88. };
  89. static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
  90. [0] = {
  91. .hwport = 0,
  92. .flags = 0,
  93. .ucon = UCON,
  94. .ulcon = ULCON,
  95. .ufcon = UFCON,
  96. .clocks = anubis_serial_clocks,
  97. .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
  98. },
  99. [1] = {
  100. .hwport = 2,
  101. .flags = 0,
  102. .ucon = UCON,
  103. .ulcon = ULCON,
  104. .ufcon = UFCON,
  105. .clocks = anubis_serial_clocks,
  106. .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
  107. },
  108. };
  109. /* NAND Flash on Anubis board */
  110. static int external_map[] = { 2 };
  111. static int chip0_map[] = { 0 };
  112. static int chip1_map[] = { 1 };
  113. static struct mtd_partition anubis_default_nand_part[] = {
  114. [0] = {
  115. .name = "Boot Agent",
  116. .size = SZ_16K,
  117. .offset = 0,
  118. },
  119. [1] = {
  120. .name = "/boot",
  121. .size = SZ_4M - SZ_16K,
  122. .offset = SZ_16K,
  123. },
  124. [2] = {
  125. .name = "user1",
  126. .offset = SZ_4M,
  127. .size = SZ_32M - SZ_4M,
  128. },
  129. [3] = {
  130. .name = "user2",
  131. .offset = SZ_32M,
  132. .size = MTDPART_SIZ_FULL,
  133. }
  134. };
  135. /* the Anubis has 3 selectable slots for nand-flash, the two
  136. * on-board chip areas, as well as the external slot.
  137. *
  138. * Note, there is no current hot-plug support for the External
  139. * socket.
  140. */
  141. static struct s3c2410_nand_set anubis_nand_sets[] = {
  142. [1] = {
  143. .name = "External",
  144. .nr_chips = 1,
  145. .nr_map = external_map,
  146. .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
  147. .partitions = anubis_default_nand_part,
  148. },
  149. [0] = {
  150. .name = "chip0",
  151. .nr_chips = 1,
  152. .nr_map = chip0_map,
  153. .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
  154. .partitions = anubis_default_nand_part,
  155. },
  156. [2] = {
  157. .name = "chip1",
  158. .nr_chips = 1,
  159. .nr_map = chip1_map,
  160. .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
  161. .partitions = anubis_default_nand_part,
  162. },
  163. };
  164. static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
  165. {
  166. unsigned int tmp;
  167. slot = set->nr_map[slot] & 3;
  168. pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
  169. slot, set, set->nr_map);
  170. tmp = __raw_readb(ANUBIS_VA_CTRL1);
  171. tmp &= ~ANUBIS_CTRL1_NANDSEL;
  172. tmp |= slot;
  173. pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
  174. __raw_writeb(tmp, ANUBIS_VA_CTRL1);
  175. }
  176. static struct s3c2410_platform_nand anubis_nand_info = {
  177. .tacls = 25,
  178. .twrph0 = 55,
  179. .twrph1 = 40,
  180. .nr_sets = ARRAY_SIZE(anubis_nand_sets),
  181. .sets = anubis_nand_sets,
  182. .select_chip = anubis_nand_select,
  183. };
  184. /* IDE channels */
  185. static struct resource anubis_ide0_resource[] = {
  186. {
  187. .start = S3C2410_CS3,
  188. .end = S3C2410_CS3 + (8*32) - 1,
  189. .flags = IORESOURCE_MEM,
  190. }, {
  191. .start = S3C2410_CS3 + (1<<26),
  192. .end = S3C2410_CS3 + (1<<26) + (8*32) - 1,
  193. .flags = IORESOURCE_MEM,
  194. }, {
  195. .start = IRQ_IDE0,
  196. .end = IRQ_IDE0,
  197. .flags = IORESOURCE_IRQ,
  198. },
  199. };
  200. static struct platform_device anubis_device_ide0 = {
  201. .name = "simtec-ide",
  202. .id = 0,
  203. .num_resources = ARRAY_SIZE(anubis_ide0_resource),
  204. .resource = anubis_ide0_resource,
  205. };
  206. static struct resource anubis_ide1_resource[] = {
  207. {
  208. .start = S3C2410_CS4,
  209. .end = S3C2410_CS4 + (8*32) - 1,
  210. .flags = IORESOURCE_MEM,
  211. }, {
  212. .start = S3C2410_CS4 + (1<<26),
  213. .end = S3C2410_CS4 + (1<<26) + (8*32) - 1,
  214. .flags = IORESOURCE_MEM,
  215. }, {
  216. .start = IRQ_IDE0,
  217. .end = IRQ_IDE0,
  218. .flags = IORESOURCE_IRQ,
  219. },
  220. };
  221. static struct platform_device anubis_device_ide1 = {
  222. .name = "simtec-ide",
  223. .id = 1,
  224. .num_resources = ARRAY_SIZE(anubis_ide1_resource),
  225. .resource = anubis_ide1_resource,
  226. };
  227. /* Standard Anubis devices */
  228. static struct platform_device *anubis_devices[] __initdata = {
  229. &s3c_device_usb,
  230. &s3c_device_wdt,
  231. &s3c_device_adc,
  232. &s3c_device_i2c,
  233. &s3c_device_rtc,
  234. &s3c_device_nand,
  235. &anubis_device_ide0,
  236. &anubis_device_ide1,
  237. };
  238. static struct clk *anubis_clocks[] = {
  239. &s3c24xx_dclk0,
  240. &s3c24xx_dclk1,
  241. &s3c24xx_clkout0,
  242. &s3c24xx_clkout1,
  243. &s3c24xx_uclk,
  244. };
  245. static struct s3c24xx_board anubis_board __initdata = {
  246. .devices = anubis_devices,
  247. .devices_count = ARRAY_SIZE(anubis_devices),
  248. .clocks = anubis_clocks,
  249. .clocks_count = ARRAY_SIZE(anubis_clocks),
  250. };
  251. static void __init anubis_map_io(void)
  252. {
  253. /* initialise the clocks */
  254. s3c24xx_dclk0.parent = NULL;
  255. s3c24xx_dclk0.rate = 12*1000*1000;
  256. s3c24xx_dclk1.parent = NULL;
  257. s3c24xx_dclk1.rate = 24*1000*1000;
  258. s3c24xx_clkout0.parent = &s3c24xx_dclk0;
  259. s3c24xx_clkout1.parent = &s3c24xx_dclk1;
  260. s3c24xx_uclk.parent = &s3c24xx_clkout1;
  261. s3c_device_nand.dev.platform_data = &anubis_nand_info;
  262. s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
  263. s3c24xx_init_clocks(0);
  264. s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
  265. s3c24xx_set_board(&anubis_board);
  266. /* ensure that the GPIO is setup */
  267. s3c2410_gpio_setpin(S3C2410_GPA0, 1);
  268. }
  269. MACHINE_START(ANUBIS, "Simtec-Anubis")
  270. /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
  271. .phys_io = S3C2410_PA_UART,
  272. .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
  273. .boot_params = S3C2410_SDRAM_PA + 0x100,
  274. .map_io = anubis_map_io,
  275. .init_irq = s3c24xx_init_irq,
  276. .timer = &s3c24xx_timer,
  277. MACHINE_END