dma.c 5.6 KB

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  1. /* linux/arch/arm/mach-s3c2440/dma.c
  2. *
  3. * Copyright (c) 2006 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2440 DMA selection
  7. *
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/sysdev.h>
  17. #include <linux/serial_core.h>
  18. #include <asm/dma.h>
  19. #include <asm/arch/dma.h>
  20. #include <asm/plat-s3c24xx/dma.h>
  21. #include <asm/plat-s3c24xx/cpu.h>
  22. #include <asm/arch/regs-serial.h>
  23. #include <asm/arch/regs-gpio.h>
  24. #include <asm/arch/regs-ac97.h>
  25. #include <asm/arch/regs-mem.h>
  26. #include <asm/arch/regs-lcd.h>
  27. #include <asm/arch/regs-sdi.h>
  28. #include <asm/arch/regs-iis.h>
  29. #include <asm/arch/regs-spi.h>
  30. static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
  31. [DMACH_XD0] = {
  32. .name = "xdreq0",
  33. .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
  34. },
  35. [DMACH_XD1] = {
  36. .name = "xdreq1",
  37. .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
  38. },
  39. [DMACH_SDI] = {
  40. .name = "sdi",
  41. .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
  42. .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
  43. .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
  44. .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
  45. .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
  46. .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
  47. },
  48. [DMACH_SPI0] = {
  49. .name = "spi0",
  50. .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
  51. .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
  52. .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
  53. },
  54. [DMACH_SPI1] = {
  55. .name = "spi1",
  56. .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
  57. .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
  58. .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
  59. },
  60. [DMACH_UART0] = {
  61. .name = "uart0",
  62. .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
  63. .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
  64. .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
  65. },
  66. [DMACH_UART1] = {
  67. .name = "uart1",
  68. .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
  69. .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
  70. .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
  71. },
  72. [DMACH_UART2] = {
  73. .name = "uart2",
  74. .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
  75. .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
  76. .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
  77. },
  78. [DMACH_TIMER] = {
  79. .name = "timer",
  80. .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
  81. .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
  82. .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
  83. },
  84. [DMACH_I2S_IN] = {
  85. .name = "i2s-sdi",
  86. .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
  87. .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
  88. .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
  89. },
  90. [DMACH_I2S_OUT] = {
  91. .name = "i2s-sdo",
  92. .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
  93. .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
  94. .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
  95. },
  96. [DMACH_PCM_IN] = {
  97. .name = "pcm-in",
  98. .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
  99. .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
  100. .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
  101. },
  102. [DMACH_PCM_OUT] = {
  103. .name = "pcm-out",
  104. .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
  105. .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
  106. .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
  107. },
  108. [DMACH_MIC_IN] = {
  109. .name = "mic-in",
  110. .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
  111. .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
  112. .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
  113. },
  114. [DMACH_USB_EP1] = {
  115. .name = "usb-ep1",
  116. .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
  117. },
  118. [DMACH_USB_EP2] = {
  119. .name = "usb-ep2",
  120. .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
  121. },
  122. [DMACH_USB_EP3] = {
  123. .name = "usb-ep3",
  124. .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
  125. },
  126. [DMACH_USB_EP4] = {
  127. .name = "usb-ep4",
  128. .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
  129. },
  130. };
  131. static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
  132. struct s3c24xx_dma_map *map)
  133. {
  134. chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
  135. }
  136. static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
  137. .select = s3c2440_dma_select,
  138. .dcon_mask = 7 << 24,
  139. .map = s3c2440_dma_mappings,
  140. .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
  141. };
  142. static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
  143. .channels = {
  144. [DMACH_SDI] = {
  145. .list = {
  146. [0] = 3 | DMA_CH_VALID,
  147. [1] = 2 | DMA_CH_VALID,
  148. [2] = 1 | DMA_CH_VALID,
  149. [3] = 0 | DMA_CH_VALID,
  150. },
  151. },
  152. [DMACH_I2S_IN] = {
  153. .list = {
  154. [0] = 1 | DMA_CH_VALID,
  155. [1] = 2 | DMA_CH_VALID,
  156. },
  157. },
  158. [DMACH_I2S_OUT] = {
  159. .list = {
  160. [0] = 2 | DMA_CH_VALID,
  161. [1] = 1 | DMA_CH_VALID,
  162. },
  163. },
  164. [DMACH_PCM_IN] = {
  165. .list = {
  166. [0] = 2 | DMA_CH_VALID,
  167. [1] = 1 | DMA_CH_VALID,
  168. },
  169. },
  170. [DMACH_PCM_OUT] = {
  171. .list = {
  172. [0] = 1 | DMA_CH_VALID,
  173. [1] = 3 | DMA_CH_VALID,
  174. },
  175. },
  176. [DMACH_MIC_IN] = {
  177. .list = {
  178. [0] = 3 | DMA_CH_VALID,
  179. [1] = 2 | DMA_CH_VALID,
  180. },
  181. },
  182. },
  183. };
  184. static int s3c2440_dma_add(struct sys_device *sysdev)
  185. {
  186. s3c2410_dma_init();
  187. s3c24xx_dma_order_set(&s3c2440_dma_order);
  188. return s3c24xx_dma_init_map(&s3c2440_dma_sel);
  189. }
  190. static struct sysdev_driver s3c2440_dma_driver = {
  191. .add = s3c2440_dma_add,
  192. };
  193. static int __init s3c2440_dma_init(void)
  194. {
  195. return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_dma_driver);
  196. }
  197. arch_initcall(s3c2440_dma_init);