irq.c 7.3 KB

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  1. /* linux/arch/arm/mach-s3c2443/irq.c
  2. *
  3. * Copyright (c) 2007 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/ioport.h>
  25. #include <linux/ptrace.h>
  26. #include <linux/sysdev.h>
  27. #include <asm/hardware.h>
  28. #include <asm/irq.h>
  29. #include <asm/io.h>
  30. #include <asm/mach/irq.h>
  31. #include <asm/arch/regs-irq.h>
  32. #include <asm/arch/regs-gpio.h>
  33. #include <asm/plat-s3c24xx/cpu.h>
  34. #include <asm/plat-s3c24xx/pm.h>
  35. #include <asm/plat-s3c24xx/irq.h>
  36. #define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
  37. static inline void s3c2443_irq_demux(unsigned int irq, unsigned int len)
  38. {
  39. unsigned int subsrc, submsk;
  40. unsigned int end;
  41. struct irq_desc *mydesc;
  42. /* read the current pending interrupts, and the mask
  43. * for what it is available */
  44. subsrc = __raw_readl(S3C2410_SUBSRCPND);
  45. submsk = __raw_readl(S3C2410_INTSUBMSK);
  46. subsrc &= ~submsk;
  47. subsrc >>= (irq - S3C2410_IRQSUB(0));
  48. subsrc &= (1 << len)-1;
  49. end = len + irq;
  50. mydesc = irq_desc + irq;
  51. for (; irq < end && subsrc; irq++) {
  52. if (subsrc & 1)
  53. desc_handle_irq(irq, mydesc);
  54. mydesc++;
  55. subsrc >>= 1;
  56. }
  57. }
  58. /* WDT/AC97 sub interrupts */
  59. static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
  60. {
  61. s3c2443_irq_demux(IRQ_S3C2443_WDT, 2);
  62. }
  63. #define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
  64. #define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
  65. static void s3c2443_irq_wdtac97_mask(unsigned int irqno)
  66. {
  67. s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
  68. }
  69. static void s3c2443_irq_wdtac97_unmask(unsigned int irqno)
  70. {
  71. s3c_irqsub_unmask(irqno, INTMSK_WDTAC97);
  72. }
  73. static void s3c2443_irq_wdtac97_ack(unsigned int irqno)
  74. {
  75. s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
  76. }
  77. static struct irq_chip s3c2443_irq_wdtac97 = {
  78. .mask = s3c2443_irq_wdtac97_mask,
  79. .unmask = s3c2443_irq_wdtac97_unmask,
  80. .ack = s3c2443_irq_wdtac97_ack,
  81. };
  82. /* LCD sub interrupts */
  83. static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
  84. {
  85. s3c2443_irq_demux(IRQ_S3C2443_LCD1, 4);
  86. }
  87. #define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
  88. #define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
  89. static void s3c2443_irq_lcd_mask(unsigned int irqno)
  90. {
  91. s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD);
  92. }
  93. static void s3c2443_irq_lcd_unmask(unsigned int irqno)
  94. {
  95. s3c_irqsub_unmask(irqno, INTMSK_LCD);
  96. }
  97. static void s3c2443_irq_lcd_ack(unsigned int irqno)
  98. {
  99. s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD);
  100. }
  101. static struct irq_chip s3c2443_irq_lcd = {
  102. .mask = s3c2443_irq_lcd_mask,
  103. .unmask = s3c2443_irq_lcd_unmask,
  104. .ack = s3c2443_irq_lcd_ack,
  105. };
  106. /* DMA sub interrupts */
  107. static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
  108. {
  109. s3c2443_irq_demux(IRQ_S3C2443_DMA0, 6);
  110. s3c2443_irq_demux(IRQ_S3C2443_DMA6, 2);
  111. }
  112. #define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
  113. #define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
  114. #define SUBMSK_DMA_NEW INTMSK(IRQ_S3C2443_DMA6, IRQ_S3C2443_DMA7)
  115. static void s3c2443_irq_dma_mask(unsigned int irqno)
  116. {
  117. if(irqno < IRQ_S3C2443_DMA6)
  118. s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA);
  119. else
  120. s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA_NEW);
  121. }
  122. static void s3c2443_irq_dma_unmask(unsigned int irqno)
  123. {
  124. s3c_irqsub_unmask(irqno, INTMSK_DMA);
  125. }
  126. static void s3c2443_irq_dma_ack(unsigned int irqno)
  127. {
  128. if(irqno < IRQ_S3C2443_DMA6)
  129. s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA);
  130. else
  131. s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA_NEW);
  132. }
  133. static struct irq_chip s3c2443_irq_dma = {
  134. .mask = s3c2443_irq_dma_mask,
  135. .unmask = s3c2443_irq_dma_unmask,
  136. .ack = s3c2443_irq_dma_ack,
  137. };
  138. /* UART3 sub interrupts */
  139. static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
  140. {
  141. s3c2443_irq_demux(IRQ_S3C2443_UART3, 3);
  142. }
  143. #define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
  144. #define SUBMSK_UART3 (0xf << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
  145. static void s3c2443_irq_uart3_mask(unsigned int irqno)
  146. {
  147. s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3);
  148. }
  149. static void s3c2443_irq_uart3_unmask(unsigned int irqno)
  150. {
  151. s3c_irqsub_unmask(irqno, INTMSK_UART3);
  152. }
  153. static void s3c2443_irq_uart3_ack(unsigned int irqno)
  154. {
  155. s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3);
  156. }
  157. static struct irq_chip s3c2443_irq_uart3 = {
  158. .mask = s3c2443_irq_uart3_mask,
  159. .unmask = s3c2443_irq_uart3_unmask,
  160. .ack = s3c2443_irq_uart3_ack,
  161. };
  162. /* CAM sub interrupts */
  163. static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
  164. {
  165. s3c2443_irq_demux(IRQ_S3C2440_CAM_C, 4);
  166. }
  167. #define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
  168. #define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P)
  169. static void s3c2443_irq_cam_mask(unsigned int irqno)
  170. {
  171. s3c_irqsub_mask(irqno, INTMSK_CAM, SUBMSK_CAM);
  172. }
  173. static void s3c2443_irq_cam_unmask(unsigned int irqno)
  174. {
  175. s3c_irqsub_unmask(irqno, INTMSK_CAM);
  176. }
  177. static void s3c2443_irq_cam_ack(unsigned int irqno)
  178. {
  179. s3c_irqsub_maskack(irqno, INTMSK_CAM, SUBMSK_CAM);
  180. }
  181. static struct irq_chip s3c2443_irq_cam = {
  182. .mask = s3c2443_irq_cam_mask,
  183. .unmask = s3c2443_irq_cam_unmask,
  184. .ack = s3c2443_irq_cam_ack,
  185. };
  186. /* IRQ initialisation code */
  187. static int __init s3c2443_add_sub(unsigned int base,
  188. void (*demux)(unsigned int,
  189. struct irq_desc *),
  190. struct irq_chip *chip,
  191. unsigned int start, unsigned int end)
  192. {
  193. unsigned int irqno;
  194. set_irq_chip(base, &s3c_irq_level_chip);
  195. set_irq_handler(base, handle_level_irq);
  196. set_irq_chained_handler(base, demux);
  197. for (irqno = start; irqno <= end; irqno++) {
  198. set_irq_chip(irqno, chip);
  199. set_irq_handler(irqno, handle_level_irq);
  200. set_irq_flags(irqno, IRQF_VALID);
  201. if(irqno == IRQ_S3C2443_DMA5)
  202. irqno += 5;
  203. }
  204. return 0;
  205. }
  206. static int s3c2443_irq_add(struct sys_device *sysdev)
  207. {
  208. printk("S3C2416: IRQ Support\n");
  209. s3c2443_add_sub(IRQ_CAM, s3c2443_irq_demux_cam, &s3c2443_irq_cam,
  210. IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P);
  211. s3c2443_add_sub(IRQ_LCD, s3c2443_irq_demux_lcd, &s3c2443_irq_lcd,
  212. IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4);
  213. s3c2443_add_sub(IRQ_S3C2443_DMA, s3c2443_irq_demux_dma,
  214. &s3c2443_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA7);
  215. s3c2443_add_sub(IRQ_S3C2443_UART3, s3c2443_irq_demux_uart3,
  216. &s3c2443_irq_uart3,
  217. IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
  218. s3c2443_add_sub(IRQ_WDT, s3c2443_irq_demux_wdtac97,
  219. &s3c2443_irq_wdtac97,
  220. IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
  221. return 0;
  222. }
  223. static struct sysdev_driver s3c2416_irq_driver = {
  224. .add = s3c2443_irq_add,
  225. };
  226. static int s3c2416_irq_init(void)
  227. {
  228. return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_irq_driver);
  229. }
  230. arch_initcall(s3c2416_irq_init);