dma.c 5.6 KB

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  1. /* linux/arch/arm/mach-s3c2416/dma.c
  2. *
  3. * Copyright (c) 2007 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. * Ryu Euiyoul <ryu.real@gmail.com>
  6. *
  7. * S3C2443 DMA selection
  8. *
  9. * http://armlinux.simtec.co.uk/
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/sysdev.h>
  18. #include <linux/serial_core.h>
  19. #include <asm/dma.h>
  20. #include <asm/arch/dma.h>
  21. #include <asm/io.h>
  22. #include <asm/plat-s3c24xx/dma.h>
  23. #include <asm/plat-s3c24xx/cpu.h>
  24. #include <asm/arch/regs-serial.h>
  25. #include <asm/arch/regs-gpio.h>
  26. #include <asm/arch/regs-ac97.h>
  27. #include <asm/arch/regs-mem.h>
  28. #include <asm/arch/regs-lcd.h>
  29. #include <asm/arch/regs-sdi.h>
  30. #include <asm/arch/regs-iis.h>
  31. #include <asm/arch/regs-spi.h>
  32. #define MAP(x) { \
  33. [0] = (x) | DMA_CH_VALID, \
  34. [1] = (x) | DMA_CH_VALID, \
  35. [2] = (x) | DMA_CH_VALID, \
  36. [3] = (x) | DMA_CH_VALID, \
  37. [4] = (x) | DMA_CH_VALID, \
  38. [5] = (x) | DMA_CH_VALID, \
  39. [6] = (x) | DMA_CH_VALID, \
  40. [7] = (x) | DMA_CH_VALID, \
  41. }
  42. static struct s3c24xx_dma_map __initdata s3c2416_dma_mappings[] = {
  43. [DMACH_XD0] = {
  44. .name = "xdreq0",
  45. .channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
  46. },
  47. [DMACH_XD1] = {
  48. .name = "xdreq1",
  49. .channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
  50. },
  51. [DMACH_SDI] = {
  52. .name = "sdi",
  53. .channels = MAP(S3C2443_DMAREQSEL_SDI),
  54. .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
  55. .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
  56. },
  57. [DMACH_SPI_TX] = {
  58. .name = "spi-tx",
  59. .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
  60. .hw_addr.from = S3C_PA_SPI_0 + S3C_SPI_TX_DATA,
  61. },
  62. [DMACH_SPI_RX] = {
  63. .name = "spi-rx",
  64. .channels = MAP(S3C2443_DMAREQSEL_SPI0RX),
  65. .hw_addr.to = S3C_PA_SPI_0 + S3C_SPI_RX_DATA,
  66. },
  67. [DMACH_SPI0] = {
  68. .name = "spi0",
  69. .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
  70. .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
  71. .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
  72. },
  73. [DMACH_SPI1] = {
  74. .name = "spi1",
  75. .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
  76. .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
  77. .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
  78. },
  79. [DMACH_UART0] = {
  80. .name = "uart0",
  81. .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
  82. .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
  83. .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
  84. },
  85. [DMACH_UART1] = {
  86. .name = "uart1",
  87. .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
  88. .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
  89. .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
  90. },
  91. [DMACH_UART2] = {
  92. .name = "uart2",
  93. .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
  94. .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
  95. .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
  96. },
  97. [DMACH_UART3] = {
  98. .name = "uart3",
  99. .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
  100. .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
  101. .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
  102. },
  103. [DMACH_UART0_SRC2] = {
  104. .name = "uart0",
  105. .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
  106. .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
  107. .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
  108. },
  109. [DMACH_UART1_SRC2] = {
  110. .name = "uart1",
  111. .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
  112. .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
  113. .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
  114. },
  115. [DMACH_UART2_SRC2] = {
  116. .name = "uart2",
  117. .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
  118. .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
  119. .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
  120. },
  121. [DMACH_UART3_SRC2] = {
  122. .name = "uart3",
  123. .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
  124. .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
  125. .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
  126. },
  127. [DMACH_TIMER] = {
  128. .name = "timer",
  129. .channels = MAP(S3C2443_DMAREQSEL_TIMER),
  130. },
  131. [DMACH_I2S_IN] = {
  132. .name = "i2s-sdi",
  133. .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
  134. .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFORX,
  135. },
  136. [DMACH_I2S_OUT] = {
  137. .name = "i2s-sdo",
  138. .channels = MAP(S3C2443_DMAREQSEL_I2STX),
  139. .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
  140. },
  141. [DMACH_I2S_IN_1] = {
  142. .name = "i2s-sdi",
  143. .channels = MAP(S3C2450_DMAREQSEL_I2SRX_1),
  144. .hw_addr.from = S3C2450_PA_IIS_1 + S3C2410_IISFIFORX,
  145. },
  146. [DMACH_I2S_OUT_1] = {
  147. .name = "i2s-sdo",
  148. .channels = MAP(S3C2450_DMAREQSEL_I2STX_1),
  149. .hw_addr.to = S3C2450_PA_IIS_1 + S3C2410_IISFIFO,
  150. },
  151. [DMACH_PCM_IN] = {
  152. .name = "pcm-in",
  153. .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
  154. .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
  155. },
  156. [DMACH_PCM_OUT] = {
  157. .name = "pcm-out",
  158. .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
  159. .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
  160. },
  161. [DMACH_MIC_IN] = {
  162. .name = "mic-in",
  163. .channels = MAP(S3C2443_DMAREQSEL_MICIN),
  164. .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
  165. },
  166. };
  167. static void s3c2416_dma_select(struct s3c2410_dma_chan *chan,
  168. struct s3c24xx_dma_map *map)
  169. {
  170. writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
  171. chan->regs + S3C2443_DMA_DMAREQSEL);
  172. }
  173. static struct s3c24xx_dma_selection __initdata s3c2416_dma_sel = {
  174. .select = s3c2416_dma_select,
  175. .dcon_mask = 0,
  176. .map = s3c2416_dma_mappings,
  177. .map_size = ARRAY_SIZE(s3c2416_dma_mappings),
  178. };
  179. static int s3c2416_dma_add(struct sys_device *sysdev)
  180. {
  181. s3c24xx_dma_init(8, IRQ_S3C2443_DMA0, 0x100);
  182. return s3c24xx_dma_init_map(&s3c2416_dma_sel);
  183. }
  184. static struct sysdev_driver s3c2416_dma_driver = {
  185. .add = s3c2416_dma_add,
  186. };
  187. static int __init s3c2416_dma_init(void)
  188. {
  189. return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_dma_driver);
  190. }
  191. arch_initcall(s3c2416_dma_init);