clock.c 16 KB

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  1. /* linux/arch/arm/mach-s3c2412/clock.c
  2. *
  3. * Copyright (c) 2006 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2412,S3C2413 Clock control support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/init.h>
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/list.h>
  26. #include <linux/errno.h>
  27. #include <linux/err.h>
  28. #include <linux/sysdev.h>
  29. #include <linux/clk.h>
  30. #include <linux/mutex.h>
  31. #include <linux/delay.h>
  32. #include <linux/serial_core.h>
  33. #include <asm/mach/map.h>
  34. #include <asm/hardware.h>
  35. #include <asm/io.h>
  36. #include <asm/arch/regs-serial.h>
  37. #include <asm/arch/regs-clock.h>
  38. #include <asm/arch/regs-gpio.h>
  39. #include <asm/plat-s3c24xx/s3c2412.h>
  40. #include <asm/plat-s3c24xx/clock.h>
  41. #include <asm/plat-s3c24xx/cpu.h>
  42. /* We currently have to assume that the system is running
  43. * from the XTPll input, and that all ***REFCLKs are being
  44. * fed from it, as we cannot read the state of OM[4] from
  45. * software.
  46. *
  47. * It would be possible for each board initialisation to
  48. * set the correct muxing at initialisation
  49. */
  50. static int s3c2412_clkcon_enable(struct clk *clk, int enable)
  51. {
  52. unsigned int clocks = clk->ctrlbit;
  53. unsigned long clkcon;
  54. clkcon = __raw_readl(S3C2410_CLKCON);
  55. if (enable)
  56. clkcon |= clocks;
  57. else
  58. clkcon &= ~clocks;
  59. __raw_writel(clkcon, S3C2410_CLKCON);
  60. return 0;
  61. }
  62. static int s3c2412_upll_enable(struct clk *clk, int enable)
  63. {
  64. unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
  65. unsigned long orig = upllcon;
  66. if (!enable)
  67. upllcon |= S3C2412_PLLCON_OFF;
  68. else
  69. upllcon &= ~S3C2412_PLLCON_OFF;
  70. __raw_writel(upllcon, S3C2410_UPLLCON);
  71. /* allow ~150uS for the PLL to settle and lock */
  72. if (enable && (orig & S3C2412_PLLCON_OFF))
  73. udelay(150);
  74. return 0;
  75. }
  76. /* clock selections */
  77. /* CPU EXTCLK input */
  78. static struct clk clk_ext = {
  79. .name = "extclk",
  80. .id = -1,
  81. };
  82. static struct clk clk_erefclk = {
  83. .name = "erefclk",
  84. .id = -1,
  85. };
  86. static struct clk clk_urefclk = {
  87. .name = "urefclk",
  88. .id = -1,
  89. };
  90. static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
  91. {
  92. unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
  93. if (parent == &clk_urefclk)
  94. clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
  95. else if (parent == &clk_upll)
  96. clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
  97. else
  98. return -EINVAL;
  99. clk->parent = parent;
  100. __raw_writel(clksrc, S3C2412_CLKSRC);
  101. return 0;
  102. }
  103. static struct clk clk_usysclk = {
  104. .name = "usysclk",
  105. .id = -1,
  106. .parent = &clk_xtal,
  107. .set_parent = s3c2412_setparent_usysclk,
  108. };
  109. static struct clk clk_mrefclk = {
  110. .name = "mrefclk",
  111. .parent = &clk_xtal,
  112. .id = -1,
  113. };
  114. static struct clk clk_mdivclk = {
  115. .name = "mdivclk",
  116. .parent = &clk_xtal,
  117. .id = -1,
  118. };
  119. static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
  120. {
  121. unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
  122. if (parent == &clk_usysclk)
  123. clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
  124. else if (parent == &clk_h)
  125. clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
  126. else
  127. return -EINVAL;
  128. clk->parent = parent;
  129. __raw_writel(clksrc, S3C2412_CLKSRC);
  130. return 0;
  131. }
  132. static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
  133. unsigned long rate)
  134. {
  135. unsigned long parent_rate = clk_get_rate(clk->parent);
  136. int div;
  137. if (rate > parent_rate)
  138. return parent_rate;
  139. div = parent_rate / rate;
  140. if (div > 2)
  141. div = 2;
  142. return parent_rate / div;
  143. }
  144. static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
  145. {
  146. unsigned long parent_rate = clk_get_rate(clk->parent);
  147. unsigned long div = __raw_readl(S3C2410_CLKDIVN);
  148. return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
  149. }
  150. static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
  151. {
  152. unsigned long parent_rate = clk_get_rate(clk->parent);
  153. unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
  154. rate = s3c2412_roundrate_usbsrc(clk, rate);
  155. if ((parent_rate / rate) == 2)
  156. clkdivn |= S3C2412_CLKDIVN_USB48DIV;
  157. else
  158. clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
  159. __raw_writel(clkdivn, S3C2410_CLKDIVN);
  160. return 0;
  161. }
  162. static struct clk clk_usbsrc = {
  163. .name = "usbsrc",
  164. .id = -1,
  165. .get_rate = s3c2412_getrate_usbsrc,
  166. .set_rate = s3c2412_setrate_usbsrc,
  167. .round_rate = s3c2412_roundrate_usbsrc,
  168. .set_parent = s3c2412_setparent_usbsrc,
  169. };
  170. static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
  171. {
  172. unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
  173. if (parent == &clk_mdivclk)
  174. clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
  175. else if (parent == &clk_upll)
  176. clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
  177. else
  178. return -EINVAL;
  179. clk->parent = parent;
  180. __raw_writel(clksrc, S3C2412_CLKSRC);
  181. return 0;
  182. }
  183. static struct clk clk_msysclk = {
  184. .name = "msysclk",
  185. .id = -1,
  186. .set_parent = s3c2412_setparent_msysclk,
  187. };
  188. /* these next clocks have an divider immediately after them,
  189. * so we can register them with their divider and leave out the
  190. * intermediate clock stage
  191. */
  192. static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
  193. unsigned long rate)
  194. {
  195. unsigned long parent_rate = clk_get_rate(clk->parent);
  196. int div;
  197. if (rate > parent_rate)
  198. return parent_rate;
  199. /* note, we remove the +/- 1 calculations as they cancel out */
  200. div = (rate / parent_rate);
  201. if (div < 1)
  202. div = 1;
  203. else if (div > 16)
  204. div = 16;
  205. return parent_rate / div;
  206. }
  207. static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
  208. {
  209. unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
  210. if (parent == &clk_erefclk)
  211. clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
  212. else if (parent == &clk_mpll)
  213. clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
  214. else
  215. return -EINVAL;
  216. clk->parent = parent;
  217. __raw_writel(clksrc, S3C2412_CLKSRC);
  218. return 0;
  219. }
  220. static unsigned long s3c2412_getrate_uart(struct clk *clk)
  221. {
  222. unsigned long parent_rate = clk_get_rate(clk->parent);
  223. unsigned long div = __raw_readl(S3C2410_CLKDIVN);
  224. div &= S3C2412_CLKDIVN_UARTDIV_MASK;
  225. div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
  226. return parent_rate / (div + 1);
  227. }
  228. static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
  229. {
  230. unsigned long parent_rate = clk_get_rate(clk->parent);
  231. unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
  232. rate = s3c2412_roundrate_clksrc(clk, rate);
  233. clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
  234. clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
  235. __raw_writel(clkdivn, S3C2410_CLKDIVN);
  236. return 0;
  237. }
  238. static struct clk clk_uart = {
  239. .name = "uartclk",
  240. .id = -1,
  241. .get_rate = s3c2412_getrate_uart,
  242. .set_rate = s3c2412_setrate_uart,
  243. .set_parent = s3c2412_setparent_uart,
  244. .round_rate = s3c2412_roundrate_clksrc,
  245. };
  246. static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
  247. {
  248. unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
  249. if (parent == &clk_erefclk)
  250. clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
  251. else if (parent == &clk_mpll)
  252. clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
  253. else
  254. return -EINVAL;
  255. clk->parent = parent;
  256. __raw_writel(clksrc, S3C2412_CLKSRC);
  257. return 0;
  258. }
  259. static unsigned long s3c2412_getrate_i2s(struct clk *clk)
  260. {
  261. unsigned long parent_rate = clk_get_rate(clk->parent);
  262. unsigned long div = __raw_readl(S3C2410_CLKDIVN);
  263. div &= S3C2412_CLKDIVN_I2SDIV_MASK;
  264. div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
  265. return parent_rate / (div + 1);
  266. }
  267. static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
  268. {
  269. unsigned long parent_rate = clk_get_rate(clk->parent);
  270. unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
  271. rate = s3c2412_roundrate_clksrc(clk, rate);
  272. clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
  273. clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
  274. __raw_writel(clkdivn, S3C2410_CLKDIVN);
  275. return 0;
  276. }
  277. static struct clk clk_i2s = {
  278. .name = "i2sclk",
  279. .id = -1,
  280. .get_rate = s3c2412_getrate_i2s,
  281. .set_rate = s3c2412_setrate_i2s,
  282. .set_parent = s3c2412_setparent_i2s,
  283. .round_rate = s3c2412_roundrate_clksrc,
  284. };
  285. static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
  286. {
  287. unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
  288. if (parent == &clk_usysclk)
  289. clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
  290. else if (parent == &clk_h)
  291. clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
  292. else
  293. return -EINVAL;
  294. clk->parent = parent;
  295. __raw_writel(clksrc, S3C2412_CLKSRC);
  296. return 0;
  297. }
  298. static unsigned long s3c2412_getrate_cam(struct clk *clk)
  299. {
  300. unsigned long parent_rate = clk_get_rate(clk->parent);
  301. unsigned long div = __raw_readl(S3C2410_CLKDIVN);
  302. div &= S3C2412_CLKDIVN_CAMDIV_MASK;
  303. div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
  304. return parent_rate / (div + 1);
  305. }
  306. static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
  307. {
  308. unsigned long parent_rate = clk_get_rate(clk->parent);
  309. unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
  310. rate = s3c2412_roundrate_clksrc(clk, rate);
  311. clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
  312. clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
  313. __raw_writel(clkdivn, S3C2410_CLKDIVN);
  314. return 0;
  315. }
  316. static struct clk clk_cam = {
  317. .name = "camif-upll", /* same as 2440 name */
  318. .id = -1,
  319. .get_rate = s3c2412_getrate_cam,
  320. .set_rate = s3c2412_setrate_cam,
  321. .set_parent = s3c2412_setparent_cam,
  322. .round_rate = s3c2412_roundrate_clksrc,
  323. };
  324. /* standard clock definitions */
  325. static struct clk init_clocks_disable[] = {
  326. {
  327. .name = "nand",
  328. .id = -1,
  329. .parent = &clk_h,
  330. .enable = s3c2412_clkcon_enable,
  331. .ctrlbit = S3C2412_CLKCON_NAND,
  332. }, {
  333. .name = "sdi",
  334. .id = -1,
  335. .parent = &clk_p,
  336. .enable = s3c2412_clkcon_enable,
  337. .ctrlbit = S3C2412_CLKCON_SDI,
  338. }, {
  339. .name = "adc",
  340. .id = -1,
  341. .parent = &clk_p,
  342. .enable = s3c2412_clkcon_enable,
  343. .ctrlbit = S3C2412_CLKCON_ADC,
  344. }, {
  345. .name = "i2c",
  346. .id = -1,
  347. .parent = &clk_p,
  348. .enable = s3c2412_clkcon_enable,
  349. .ctrlbit = S3C2412_CLKCON_IIC,
  350. }, {
  351. .name = "iis",
  352. .id = -1,
  353. .parent = &clk_p,
  354. .enable = s3c2412_clkcon_enable,
  355. .ctrlbit = S3C2412_CLKCON_IIS,
  356. }, {
  357. .name = "spi",
  358. .id = -1,
  359. .parent = &clk_p,
  360. .enable = s3c2412_clkcon_enable,
  361. .ctrlbit = S3C2412_CLKCON_SPI,
  362. }
  363. };
  364. static struct clk init_clocks[] = {
  365. {
  366. .name = "dma",
  367. .id = 0,
  368. .parent = &clk_h,
  369. .enable = s3c2412_clkcon_enable,
  370. .ctrlbit = S3C2412_CLKCON_DMA0,
  371. }, {
  372. .name = "dma",
  373. .id = 1,
  374. .parent = &clk_h,
  375. .enable = s3c2412_clkcon_enable,
  376. .ctrlbit = S3C2412_CLKCON_DMA1,
  377. }, {
  378. .name = "dma",
  379. .id = 2,
  380. .parent = &clk_h,
  381. .enable = s3c2412_clkcon_enable,
  382. .ctrlbit = S3C2412_CLKCON_DMA2,
  383. }, {
  384. .name = "dma",
  385. .id = 3,
  386. .parent = &clk_h,
  387. .enable = s3c2412_clkcon_enable,
  388. .ctrlbit = S3C2412_CLKCON_DMA3,
  389. }, {
  390. .name = "lcd",
  391. .id = -1,
  392. .parent = &clk_h,
  393. .enable = s3c2412_clkcon_enable,
  394. .ctrlbit = S3C2412_CLKCON_LCDC,
  395. }, {
  396. .name = "gpio",
  397. .id = -1,
  398. .parent = &clk_p,
  399. .enable = s3c2412_clkcon_enable,
  400. .ctrlbit = S3C2412_CLKCON_GPIO,
  401. }, {
  402. .name = "usb-host",
  403. .id = -1,
  404. .parent = &clk_h,
  405. .enable = s3c2412_clkcon_enable,
  406. .ctrlbit = S3C2412_CLKCON_USBH,
  407. }, {
  408. .name = "usb-device",
  409. .id = -1,
  410. .parent = &clk_h,
  411. .enable = s3c2412_clkcon_enable,
  412. .ctrlbit = S3C2412_CLKCON_USBD,
  413. }, {
  414. .name = "timers",
  415. .id = -1,
  416. .parent = &clk_p,
  417. .enable = s3c2412_clkcon_enable,
  418. .ctrlbit = S3C2412_CLKCON_PWMT,
  419. }, {
  420. .name = "uart",
  421. .id = 0,
  422. .parent = &clk_p,
  423. .enable = s3c2412_clkcon_enable,
  424. .ctrlbit = S3C2412_CLKCON_UART0,
  425. }, {
  426. .name = "uart",
  427. .id = 1,
  428. .parent = &clk_p,
  429. .enable = s3c2412_clkcon_enable,
  430. .ctrlbit = S3C2412_CLKCON_UART1,
  431. }, {
  432. .name = "uart",
  433. .id = 2,
  434. .parent = &clk_p,
  435. .enable = s3c2412_clkcon_enable,
  436. .ctrlbit = S3C2412_CLKCON_UART2,
  437. }, {
  438. .name = "rtc",
  439. .id = -1,
  440. .parent = &clk_p,
  441. .enable = s3c2412_clkcon_enable,
  442. .ctrlbit = S3C2412_CLKCON_RTC,
  443. }, {
  444. .name = "watchdog",
  445. .id = -1,
  446. .parent = &clk_p,
  447. .ctrlbit = 0,
  448. }, {
  449. .name = "usb-bus-gadget",
  450. .id = -1,
  451. .parent = &clk_usb_bus,
  452. .enable = s3c2412_clkcon_enable,
  453. .ctrlbit = S3C2412_CLKCON_USB_DEV48,
  454. }, {
  455. .name = "usb-bus-host",
  456. .id = -1,
  457. .parent = &clk_usb_bus,
  458. .enable = s3c2412_clkcon_enable,
  459. .ctrlbit = S3C2412_CLKCON_USB_HOST48,
  460. }
  461. };
  462. /* clocks to add where we need to check their parentage */
  463. struct clk_init {
  464. struct clk *clk;
  465. unsigned int bit;
  466. struct clk *src_0;
  467. struct clk *src_1;
  468. };
  469. static struct clk_init clks_src[] __initdata = {
  470. {
  471. .clk = &clk_usysclk,
  472. .bit = S3C2412_CLKSRC_USBCLK_HCLK,
  473. .src_0 = &clk_urefclk,
  474. .src_1 = &clk_upll,
  475. }, {
  476. .clk = &clk_i2s,
  477. .bit = S3C2412_CLKSRC_I2SCLK_MPLL,
  478. .src_0 = &clk_erefclk,
  479. .src_1 = &clk_mpll,
  480. }, {
  481. .clk = &clk_cam,
  482. .bit = S3C2412_CLKSRC_CAMCLK_HCLK,
  483. .src_0 = &clk_usysclk,
  484. .src_1 = &clk_h,
  485. }, {
  486. .clk = &clk_msysclk,
  487. .bit = S3C2412_CLKSRC_MSYSCLK_MPLL,
  488. .src_0 = &clk_mdivclk,
  489. .src_1 = &clk_mpll,
  490. }, {
  491. .clk = &clk_uart,
  492. .bit = S3C2412_CLKSRC_UARTCLK_MPLL,
  493. .src_0 = &clk_erefclk,
  494. .src_1 = &clk_mpll,
  495. }, {
  496. .clk = &clk_usbsrc,
  497. .bit = S3C2412_CLKSRC_USBCLK_HCLK,
  498. .src_0 = &clk_usysclk,
  499. .src_1 = &clk_h,
  500. },
  501. };
  502. /* s3c2412_clk_initparents
  503. *
  504. * Initialise the parents for the clocks that we get at start-time
  505. */
  506. static void __init s3c2412_clk_initparents(void)
  507. {
  508. unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
  509. struct clk_init *cip = clks_src;
  510. struct clk *src;
  511. int ptr;
  512. int ret;
  513. for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
  514. ret = s3c24xx_register_clock(cip->clk);
  515. if (ret < 0) {
  516. printk(KERN_ERR "Failed to register clock %s (%d)\n",
  517. cip->clk->name, ret);
  518. }
  519. src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
  520. printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
  521. clk_set_parent(cip->clk, src);
  522. }
  523. }
  524. /* clocks to add straight away */
  525. static struct clk *clks[] __initdata = {
  526. &clk_ext,
  527. &clk_usb_bus,
  528. &clk_erefclk,
  529. &clk_urefclk,
  530. &clk_mrefclk,
  531. };
  532. int __init s3c2412_baseclk_add(void)
  533. {
  534. unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
  535. struct clk *clkp;
  536. int ret;
  537. int ptr;
  538. clk_upll.enable = s3c2412_upll_enable;
  539. clk_usb_bus.parent = &clk_usbsrc;
  540. clk_usb_bus.rate = 0x0;
  541. s3c2412_clk_initparents();
  542. for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
  543. clkp = clks[ptr];
  544. ret = s3c24xx_register_clock(clkp);
  545. if (ret < 0) {
  546. printk(KERN_ERR "Failed to register clock %s (%d)\n",
  547. clkp->name, ret);
  548. }
  549. }
  550. /* ensure usb bus clock is within correct rate of 48MHz */
  551. if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
  552. printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
  553. /* for the moment, let's use the UPLL, and see if we can
  554. * get 48MHz */
  555. clk_set_parent(&clk_usysclk, &clk_upll);
  556. clk_set_parent(&clk_usbsrc, &clk_usysclk);
  557. clk_set_rate(&clk_usbsrc, 48*1000*1000);
  558. }
  559. printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
  560. (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
  561. print_mhz(clk_get_rate(&clk_upll)),
  562. print_mhz(clk_get_rate(&clk_usb_bus)));
  563. /* register clocks from clock array */
  564. clkp = init_clocks;
  565. for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
  566. /* ensure that we note the clock state */
  567. clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
  568. ret = s3c24xx_register_clock(clkp);
  569. if (ret < 0) {
  570. printk(KERN_ERR "Failed to register clock %s (%d)\n",
  571. clkp->name, ret);
  572. }
  573. }
  574. /* We must be careful disabling the clocks we are not intending to
  575. * be using at boot time, as subsytems such as the LCD which do
  576. * their own DMA requests to the bus can cause the system to lockup
  577. * if they where in the middle of requesting bus access.
  578. *
  579. * Disabling the LCD clock if the LCD is active is very dangerous,
  580. * and therefore the bootloader should be careful to not enable
  581. * the LCD clock if it is not needed.
  582. */
  583. /* install (and disable) the clocks we do not need immediately */
  584. clkp = init_clocks_disable;
  585. for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
  586. ret = s3c24xx_register_clock(clkp);
  587. if (ret < 0) {
  588. printk(KERN_ERR "Failed to register clock %s (%d)\n",
  589. clkp->name, ret);
  590. }
  591. s3c2412_clkcon_enable(clkp, 0);
  592. }
  593. return 0;
  594. }