mach-bast.c 13 KB

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  1. /* linux/arch/arm/mach-s3c2410/mach-bast.c
  2. *
  3. * Copyright (c) 2003-2005 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * http://www.simtec.co.uk/products/EB2410ITX/
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/types.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/list.h>
  16. #include <linux/timer.h>
  17. #include <linux/init.h>
  18. #include <linux/serial_core.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/dm9000.h>
  21. #include <asm/mach/arch.h>
  22. #include <asm/mach/map.h>
  23. #include <asm/mach/irq.h>
  24. #include <asm/arch/bast-map.h>
  25. #include <asm/arch/bast-irq.h>
  26. #include <asm/arch/bast-cpld.h>
  27. #include <asm/hardware.h>
  28. #include <asm/io.h>
  29. #include <asm/irq.h>
  30. #include <asm/mach-types.h>
  31. //#include <asm/debug-ll.h>
  32. #include <asm/arch/regs-serial.h>
  33. #include <asm/arch/regs-gpio.h>
  34. #include <asm/arch/regs-mem.h>
  35. #include <asm/arch/regs-lcd.h>
  36. #include <asm/arch/nand.h>
  37. #include <asm/arch/iic.h>
  38. #include <asm/arch/fb.h>
  39. #include <linux/mtd/mtd.h>
  40. #include <linux/mtd/nand.h>
  41. #include <linux/mtd/nand_ecc.h>
  42. #include <linux/mtd/partitions.h>
  43. #include <linux/serial_8250.h>
  44. #include <asm/plat-s3c24xx/clock.h>
  45. #include <asm/plat-s3c24xx/devs.h>
  46. #include <asm/plat-s3c24xx/cpu.h>
  47. #include "usb-simtec.h"
  48. #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
  49. /* macros for virtual address mods for the io space entries */
  50. #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
  51. #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
  52. #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
  53. #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
  54. /* macros to modify the physical addresses for io space */
  55. #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
  56. #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
  57. #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
  58. #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
  59. static struct map_desc bast_iodesc[] __initdata = {
  60. /* ISA IO areas */
  61. {
  62. .virtual = (u32)S3C24XX_VA_ISA_BYTE,
  63. .pfn = PA_CS2(BAST_PA_ISAIO),
  64. .length = SZ_16M,
  65. .type = MT_DEVICE,
  66. }, {
  67. .virtual = (u32)S3C24XX_VA_ISA_WORD,
  68. .pfn = PA_CS3(BAST_PA_ISAIO),
  69. .length = SZ_16M,
  70. .type = MT_DEVICE,
  71. },
  72. /* bast CPLD control registers, and external interrupt controls */
  73. {
  74. .virtual = (u32)BAST_VA_CTRL1,
  75. .pfn = __phys_to_pfn(BAST_PA_CTRL1),
  76. .length = SZ_1M,
  77. .type = MT_DEVICE,
  78. }, {
  79. .virtual = (u32)BAST_VA_CTRL2,
  80. .pfn = __phys_to_pfn(BAST_PA_CTRL2),
  81. .length = SZ_1M,
  82. .type = MT_DEVICE,
  83. }, {
  84. .virtual = (u32)BAST_VA_CTRL3,
  85. .pfn = __phys_to_pfn(BAST_PA_CTRL3),
  86. .length = SZ_1M,
  87. .type = MT_DEVICE,
  88. }, {
  89. .virtual = (u32)BAST_VA_CTRL4,
  90. .pfn = __phys_to_pfn(BAST_PA_CTRL4),
  91. .length = SZ_1M,
  92. .type = MT_DEVICE,
  93. },
  94. /* PC104 IRQ mux */
  95. {
  96. .virtual = (u32)BAST_VA_PC104_IRQREQ,
  97. .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
  98. .length = SZ_1M,
  99. .type = MT_DEVICE,
  100. }, {
  101. .virtual = (u32)BAST_VA_PC104_IRQRAW,
  102. .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
  103. .length = SZ_1M,
  104. .type = MT_DEVICE,
  105. }, {
  106. .virtual = (u32)BAST_VA_PC104_IRQMASK,
  107. .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
  108. .length = SZ_1M,
  109. .type = MT_DEVICE,
  110. },
  111. /* peripheral space... one for each of fast/slow/byte/16bit */
  112. /* note, ide is only decoded in word space, even though some registers
  113. * are only 8bit */
  114. /* slow, byte */
  115. { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
  116. { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
  117. { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
  118. { VA_C2(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
  119. { VA_C2(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
  120. { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  121. { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
  122. /* slow, word */
  123. { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
  124. { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
  125. { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
  126. { VA_C3(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
  127. { VA_C3(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
  128. { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  129. { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
  130. /* fast, byte */
  131. { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
  132. { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
  133. { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
  134. { VA_C4(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
  135. { VA_C4(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
  136. { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  137. { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
  138. /* fast, word */
  139. { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
  140. { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
  141. { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
  142. { VA_C5(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
  143. { VA_C5(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
  144. { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  145. { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
  146. };
  147. #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  148. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  149. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  150. static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
  151. [0] = {
  152. .name = "uclk",
  153. .divisor = 1,
  154. .min_baud = 0,
  155. .max_baud = 0,
  156. },
  157. [1] = {
  158. .name = "pclk",
  159. .divisor = 1,
  160. .min_baud = 0,
  161. .max_baud = 0,
  162. }
  163. };
  164. static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
  165. [0] = {
  166. .hwport = 0,
  167. .flags = 0,
  168. .ucon = UCON,
  169. .ulcon = ULCON,
  170. .ufcon = UFCON,
  171. .clocks = bast_serial_clocks,
  172. .clocks_size = ARRAY_SIZE(bast_serial_clocks),
  173. },
  174. [1] = {
  175. .hwport = 1,
  176. .flags = 0,
  177. .ucon = UCON,
  178. .ulcon = ULCON,
  179. .ufcon = UFCON,
  180. .clocks = bast_serial_clocks,
  181. .clocks_size = ARRAY_SIZE(bast_serial_clocks),
  182. },
  183. /* port 2 is not actually used */
  184. [2] = {
  185. .hwport = 2,
  186. .flags = 0,
  187. .ucon = UCON,
  188. .ulcon = ULCON,
  189. .ufcon = UFCON,
  190. .clocks = bast_serial_clocks,
  191. .clocks_size = ARRAY_SIZE(bast_serial_clocks),
  192. }
  193. };
  194. /* NOR Flash on BAST board */
  195. static struct resource bast_nor_resource[] = {
  196. [0] = {
  197. .start = S3C2410_CS1 + 0x4000000,
  198. .end = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
  199. .flags = IORESOURCE_MEM,
  200. }
  201. };
  202. static struct platform_device bast_device_nor = {
  203. .name = "bast-nor",
  204. .id = -1,
  205. .num_resources = ARRAY_SIZE(bast_nor_resource),
  206. .resource = bast_nor_resource,
  207. };
  208. /* NAND Flash on BAST board */
  209. static int smartmedia_map[] = { 0 };
  210. static int chip0_map[] = { 1 };
  211. static int chip1_map[] = { 2 };
  212. static int chip2_map[] = { 3 };
  213. static struct mtd_partition bast_default_nand_part[] = {
  214. [0] = {
  215. .name = "Boot Agent",
  216. .size = SZ_16K,
  217. .offset = 0,
  218. },
  219. [1] = {
  220. .name = "/boot",
  221. .size = SZ_4M - SZ_16K,
  222. .offset = SZ_16K,
  223. },
  224. [2] = {
  225. .name = "user",
  226. .offset = SZ_4M,
  227. .size = MTDPART_SIZ_FULL,
  228. }
  229. };
  230. /* the bast has 4 selectable slots for nand-flash, the three
  231. * on-board chip areas, as well as the external SmartMedia
  232. * slot.
  233. *
  234. * Note, there is no current hot-plug support for the SmartMedia
  235. * socket.
  236. */
  237. static struct s3c2410_nand_set bast_nand_sets[] = {
  238. [0] = {
  239. .name = "SmartMedia",
  240. .nr_chips = 1,
  241. .nr_map = smartmedia_map,
  242. .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
  243. .partitions = bast_default_nand_part,
  244. },
  245. [1] = {
  246. .name = "chip0",
  247. .nr_chips = 1,
  248. .nr_map = chip0_map,
  249. .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
  250. .partitions = bast_default_nand_part,
  251. },
  252. [2] = {
  253. .name = "chip1",
  254. .nr_chips = 1,
  255. .nr_map = chip1_map,
  256. .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
  257. .partitions = bast_default_nand_part,
  258. },
  259. [3] = {
  260. .name = "chip2",
  261. .nr_chips = 1,
  262. .nr_map = chip2_map,
  263. .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
  264. .partitions = bast_default_nand_part,
  265. }
  266. };
  267. static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
  268. {
  269. unsigned int tmp;
  270. slot = set->nr_map[slot] & 3;
  271. pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
  272. slot, set, set->nr_map);
  273. tmp = __raw_readb(BAST_VA_CTRL2);
  274. tmp &= BAST_CPLD_CTLR2_IDERST;
  275. tmp |= slot;
  276. tmp |= BAST_CPLD_CTRL2_WNAND;
  277. pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
  278. __raw_writeb(tmp, BAST_VA_CTRL2);
  279. }
  280. static struct s3c2410_platform_nand bast_nand_info = {
  281. .tacls = 30,
  282. .twrph0 = 60,
  283. .twrph1 = 60,
  284. .nr_sets = ARRAY_SIZE(bast_nand_sets),
  285. .sets = bast_nand_sets,
  286. .select_chip = bast_nand_select,
  287. };
  288. /* DM9000 */
  289. static struct resource bast_dm9k_resource[] = {
  290. [0] = {
  291. .start = S3C2410_CS5 + BAST_PA_DM9000,
  292. .end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
  293. .flags = IORESOURCE_MEM,
  294. },
  295. [1] = {
  296. .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
  297. .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
  298. .flags = IORESOURCE_MEM,
  299. },
  300. [2] = {
  301. .start = IRQ_DM9000,
  302. .end = IRQ_DM9000,
  303. .flags = IORESOURCE_IRQ,
  304. }
  305. };
  306. /* for the moment we limit ourselves to 16bit IO until some
  307. * better IO routines can be written and tested
  308. */
  309. static struct dm9000_plat_data bast_dm9k_platdata = {
  310. .flags = DM9000_PLATF_16BITONLY,
  311. };
  312. static struct platform_device bast_device_dm9k = {
  313. .name = "dm9000",
  314. .id = 0,
  315. .num_resources = ARRAY_SIZE(bast_dm9k_resource),
  316. .resource = bast_dm9k_resource,
  317. .dev = {
  318. .platform_data = &bast_dm9k_platdata,
  319. }
  320. };
  321. /* serial devices */
  322. #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
  323. #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
  324. #define SERIAL_CLK (1843200)
  325. static struct plat_serial8250_port bast_sio_data[] = {
  326. [0] = {
  327. .mapbase = SERIAL_BASE + 0x2f8,
  328. .irq = IRQ_PCSERIAL1,
  329. .flags = SERIAL_FLAGS,
  330. .iotype = UPIO_MEM,
  331. .regshift = 0,
  332. .uartclk = SERIAL_CLK,
  333. },
  334. [1] = {
  335. .mapbase = SERIAL_BASE + 0x3f8,
  336. .irq = IRQ_PCSERIAL2,
  337. .flags = SERIAL_FLAGS,
  338. .iotype = UPIO_MEM,
  339. .regshift = 0,
  340. .uartclk = SERIAL_CLK,
  341. },
  342. { }
  343. };
  344. static struct platform_device bast_sio = {
  345. .name = "serial8250",
  346. .id = PLAT8250_DEV_PLATFORM,
  347. .dev = {
  348. .platform_data = &bast_sio_data,
  349. },
  350. };
  351. /* we have devices on the bus which cannot work much over the
  352. * standard 100KHz i2c bus frequency
  353. */
  354. static struct s3c2410_platform_i2c bast_i2c_info = {
  355. .flags = 0,
  356. .slave_addr = 0x10,
  357. .bus_freq = 100*1000,
  358. .max_freq = 130*1000,
  359. };
  360. static struct s3c2410fb_mach_info __initdata bast_lcd_info = {
  361. .width = 640,
  362. .height = 480,
  363. .xres = {
  364. .min = 320,
  365. .max = 1024,
  366. .defval = 640,
  367. },
  368. .yres = {
  369. .min = 240,
  370. .max = 600,
  371. .defval = 480,
  372. },
  373. .bpp = {
  374. .min = 4,
  375. .max = 16,
  376. .defval = 8,
  377. },
  378. .regs = {
  379. .lcdcon1 = 0x00000176,
  380. .lcdcon2 = 0x1d77c7c2,
  381. .lcdcon3 = 0x013a7f13,
  382. .lcdcon4 = 0x00000057,
  383. .lcdcon5 = 0x00014b02,
  384. }
  385. };
  386. /* Standard BAST devices */
  387. static struct platform_device *bast_devices[] __initdata = {
  388. &s3c_device_usb,
  389. &s3c_device_lcd,
  390. &s3c_device_wdt,
  391. &s3c_device_i2c,
  392. &s3c_device_iis,
  393. &s3c_device_rtc,
  394. &s3c_device_nand,
  395. &bast_device_nor,
  396. &bast_device_dm9k,
  397. &bast_sio,
  398. };
  399. static struct clk *bast_clocks[] = {
  400. &s3c24xx_dclk0,
  401. &s3c24xx_dclk1,
  402. &s3c24xx_clkout0,
  403. &s3c24xx_clkout1,
  404. &s3c24xx_uclk,
  405. };
  406. static struct s3c24xx_board bast_board __initdata = {
  407. .devices = bast_devices,
  408. .devices_count = ARRAY_SIZE(bast_devices),
  409. .clocks = bast_clocks,
  410. .clocks_count = ARRAY_SIZE(bast_clocks),
  411. };
  412. static void __init bast_map_io(void)
  413. {
  414. /* initialise the clocks */
  415. s3c24xx_dclk0.parent = NULL;
  416. s3c24xx_dclk0.rate = 12*1000*1000;
  417. s3c24xx_dclk1.parent = NULL;
  418. s3c24xx_dclk1.rate = 24*1000*1000;
  419. s3c24xx_clkout0.parent = &s3c24xx_dclk0;
  420. s3c24xx_clkout1.parent = &s3c24xx_dclk1;
  421. s3c24xx_uclk.parent = &s3c24xx_clkout1;
  422. s3c_device_nand.dev.platform_data = &bast_nand_info;
  423. s3c_device_i2c.dev.platform_data = &bast_i2c_info;
  424. s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
  425. s3c24xx_init_clocks(0);
  426. s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
  427. s3c24xx_set_board(&bast_board);
  428. usb_simtec_init();
  429. }
  430. static void __init bast_init(void)
  431. {
  432. s3c24xx_fb_set_platdata(&bast_lcd_info);
  433. }
  434. MACHINE_START(BAST, "Simtec-BAST")
  435. /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
  436. .phys_io = S3C2410_PA_UART,
  437. .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
  438. .boot_params = S3C2410_SDRAM_PA + 0x100,
  439. .map_io = bast_map_io,
  440. .init_irq = s3c24xx_init_irq,
  441. .init_machine = bast_init,
  442. .timer = &s3c24xx_timer,
  443. MACHINE_END