dma.c 4.8 KB

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  1. /* linux/arch/arm/mach-s3c2410/dma.c
  2. *
  3. * Copyright (c) 2006 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 DMA selection
  7. *
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/sysdev.h>
  17. #include <linux/serial_core.h>
  18. #include <asm/dma.h>
  19. #include <asm/arch/dma.h>
  20. #include <asm/plat-s3c24xx/cpu.h>
  21. #include <asm/plat-s3c24xx/dma.h>
  22. #include <asm/arch/regs-serial.h>
  23. #include <asm/arch/regs-gpio.h>
  24. #include <asm/arch/regs-ac97.h>
  25. #include <asm/arch/regs-mem.h>
  26. #include <asm/arch/regs-lcd.h>
  27. #include <asm/arch/regs-sdi.h>
  28. #include <asm/arch/regs-iis.h>
  29. #include <asm/arch/regs-spi.h>
  30. static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
  31. [DMACH_XD0] = {
  32. .name = "xdreq0",
  33. .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
  34. },
  35. [DMACH_XD1] = {
  36. .name = "xdreq1",
  37. .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
  38. },
  39. [DMACH_SDI] = {
  40. .name = "sdi",
  41. .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
  42. .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
  43. .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
  44. .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
  45. .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
  46. },
  47. [DMACH_SPI0] = {
  48. .name = "spi0",
  49. .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
  50. .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
  51. .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
  52. },
  53. [DMACH_SPI1] = {
  54. .name = "spi1",
  55. .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
  56. .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
  57. .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
  58. },
  59. [DMACH_UART0] = {
  60. .name = "uart0",
  61. .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
  62. .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
  63. .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
  64. },
  65. [DMACH_UART1] = {
  66. .name = "uart1",
  67. .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
  68. .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
  69. .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
  70. },
  71. [DMACH_UART2] = {
  72. .name = "uart2",
  73. .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
  74. .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
  75. .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
  76. },
  77. [DMACH_TIMER] = {
  78. .name = "timer",
  79. .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
  80. .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
  81. .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
  82. },
  83. [DMACH_I2S_IN] = {
  84. .name = "i2s-sdi",
  85. .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
  86. .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
  87. .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
  88. },
  89. [DMACH_I2S_OUT] = {
  90. .name = "i2s-sdo",
  91. .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
  92. .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
  93. },
  94. [DMACH_USB_EP1] = {
  95. .name = "usb-ep1",
  96. .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
  97. },
  98. [DMACH_USB_EP2] = {
  99. .name = "usb-ep2",
  100. .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
  101. },
  102. [DMACH_USB_EP3] = {
  103. .name = "usb-ep3",
  104. .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
  105. },
  106. [DMACH_USB_EP4] = {
  107. .name = "usb-ep4",
  108. .channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
  109. },
  110. };
  111. static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
  112. struct s3c24xx_dma_map *map)
  113. {
  114. chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
  115. }
  116. static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
  117. .select = s3c2410_dma_select,
  118. .dcon_mask = 7 << 24,
  119. .map = s3c2410_dma_mappings,
  120. .map_size = ARRAY_SIZE(s3c2410_dma_mappings),
  121. };
  122. static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
  123. .channels = {
  124. [DMACH_SDI] = {
  125. .list = {
  126. [0] = 3 | DMA_CH_VALID,
  127. [1] = 2 | DMA_CH_VALID,
  128. [2] = 0 | DMA_CH_VALID,
  129. },
  130. },
  131. [DMACH_I2S_IN] = {
  132. .list = {
  133. [0] = 1 | DMA_CH_VALID,
  134. [1] = 2 | DMA_CH_VALID,
  135. },
  136. },
  137. },
  138. };
  139. static int s3c2410_dma_add(struct sys_device *sysdev)
  140. {
  141. s3c2410_dma_init();
  142. s3c24xx_dma_order_set(&s3c2410_dma_order);
  143. return s3c24xx_dma_init_map(&s3c2410_dma_sel);
  144. }
  145. #if defined(CONFIG_CPU_S3C2410)
  146. static struct sysdev_driver s3c2410_dma_driver = {
  147. .add = s3c2410_dma_add,
  148. };
  149. static int __init s3c2410_dma_drvinit(void)
  150. {
  151. return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver);
  152. }
  153. arch_initcall(s3c2410_dma_drvinit);
  154. #endif
  155. #if defined(CONFIG_CPU_S3C2442)
  156. /* S3C2442 DMA contains the same selection table as the S3C2410 */
  157. static struct sysdev_driver s3c2442_dma_driver = {
  158. .add = s3c2410_dma_add,
  159. };
  160. static int __init s3c2442_dma_drvinit(void)
  161. {
  162. return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver);
  163. }
  164. arch_initcall(s3c2442_dma_drvinit);
  165. #endif