clock.c 6.6 KB

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  1. /* linux/arch/arm/mach-s3c2410/clock.c
  2. *
  3. * Copyright (c) 2006 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410,S3C2440,S3C2442 Clock control support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/init.h>
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/list.h>
  26. #include <linux/errno.h>
  27. #include <linux/err.h>
  28. #include <linux/sysdev.h>
  29. #include <linux/clk.h>
  30. #include <linux/mutex.h>
  31. #include <linux/delay.h>
  32. #include <linux/serial_core.h>
  33. #include <asm/mach/map.h>
  34. #include <asm/hardware.h>
  35. #include <asm/io.h>
  36. #include <asm/arch/regs-serial.h>
  37. #include <asm/arch/regs-clock.h>
  38. #include <asm/arch/regs-gpio.h>
  39. #include <asm/plat-s3c24xx/s3c2410.h>
  40. #include <asm/plat-s3c24xx/clock.h>
  41. #include <asm/plat-s3c24xx/cpu.h>
  42. int s3c2410_clkcon_enable(struct clk *clk, int enable)
  43. {
  44. unsigned int clocks = clk->ctrlbit;
  45. unsigned long clkcon;
  46. clkcon = __raw_readl(S3C2410_CLKCON);
  47. if (enable)
  48. clkcon |= clocks;
  49. else
  50. clkcon &= ~clocks;
  51. /* ensure none of the special function bits set */
  52. clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
  53. __raw_writel(clkcon, S3C2410_CLKCON);
  54. return 0;
  55. }
  56. static int s3c2410_upll_enable(struct clk *clk, int enable)
  57. {
  58. unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
  59. unsigned long orig = clkslow;
  60. if (enable)
  61. clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
  62. else
  63. clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
  64. __raw_writel(clkslow, S3C2410_CLKSLOW);
  65. /* if we started the UPLL, then allow to settle */
  66. if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
  67. udelay(200);
  68. return 0;
  69. }
  70. /* standard clock definitions */
  71. static struct clk init_clocks_disable[] = {
  72. {
  73. .name = "nand",
  74. .id = -1,
  75. .parent = &clk_h,
  76. .enable = s3c2410_clkcon_enable,
  77. .ctrlbit = S3C2410_CLKCON_NAND,
  78. }, {
  79. .name = "sdi",
  80. .id = -1,
  81. .parent = &clk_p,
  82. .enable = s3c2410_clkcon_enable,
  83. .ctrlbit = S3C2410_CLKCON_SDI,
  84. }, {
  85. .name = "adc",
  86. .id = -1,
  87. .parent = &clk_p,
  88. .enable = s3c2410_clkcon_enable,
  89. .ctrlbit = S3C2410_CLKCON_ADC,
  90. }, {
  91. .name = "i2c",
  92. .id = -1,
  93. .parent = &clk_p,
  94. .enable = s3c2410_clkcon_enable,
  95. .ctrlbit = S3C2410_CLKCON_IIC,
  96. }, {
  97. .name = "iis",
  98. .id = -1,
  99. .parent = &clk_p,
  100. .enable = s3c2410_clkcon_enable,
  101. .ctrlbit = S3C2410_CLKCON_IIS,
  102. }, {
  103. .name = "spi",
  104. .id = -1,
  105. .parent = &clk_p,
  106. .enable = s3c2410_clkcon_enable,
  107. .ctrlbit = S3C2410_CLKCON_SPI,
  108. }
  109. };
  110. static struct clk init_clocks[] = {
  111. {
  112. .name = "lcd",
  113. .id = -1,
  114. .parent = &clk_h,
  115. .enable = s3c2410_clkcon_enable,
  116. .ctrlbit = S3C2410_CLKCON_LCDC,
  117. }, {
  118. .name = "gpio",
  119. .id = -1,
  120. .parent = &clk_p,
  121. .enable = s3c2410_clkcon_enable,
  122. .ctrlbit = S3C2410_CLKCON_GPIO,
  123. }, {
  124. .name = "usb-host",
  125. .id = -1,
  126. .parent = &clk_h,
  127. .enable = s3c2410_clkcon_enable,
  128. .ctrlbit = S3C2410_CLKCON_USBH,
  129. }, {
  130. .name = "usb-device",
  131. .id = -1,
  132. .parent = &clk_h,
  133. .enable = s3c2410_clkcon_enable,
  134. .ctrlbit = S3C2410_CLKCON_USBD,
  135. }, {
  136. .name = "timers",
  137. .id = -1,
  138. .parent = &clk_p,
  139. .enable = s3c2410_clkcon_enable,
  140. .ctrlbit = S3C2410_CLKCON_PWMT,
  141. }, {
  142. .name = "uart",
  143. .id = 0,
  144. .parent = &clk_p,
  145. .enable = s3c2410_clkcon_enable,
  146. .ctrlbit = S3C2410_CLKCON_UART0,
  147. }, {
  148. .name = "uart",
  149. .id = 1,
  150. .parent = &clk_p,
  151. .enable = s3c2410_clkcon_enable,
  152. .ctrlbit = S3C2410_CLKCON_UART1,
  153. }, {
  154. .name = "uart",
  155. .id = 2,
  156. .parent = &clk_p,
  157. .enable = s3c2410_clkcon_enable,
  158. .ctrlbit = S3C2410_CLKCON_UART2,
  159. }, {
  160. .name = "rtc",
  161. .id = -1,
  162. .parent = &clk_p,
  163. .enable = s3c2410_clkcon_enable,
  164. .ctrlbit = S3C2410_CLKCON_RTC,
  165. }, {
  166. .name = "watchdog",
  167. .id = -1,
  168. .parent = &clk_p,
  169. .ctrlbit = 0,
  170. }, {
  171. .name = "usb-bus-host",
  172. .id = -1,
  173. .parent = &clk_usb_bus,
  174. }, {
  175. .name = "usb-bus-gadget",
  176. .id = -1,
  177. .parent = &clk_usb_bus,
  178. },
  179. };
  180. /* s3c2410_baseclk_add()
  181. *
  182. * Add all the clocks used by the s3c2410 or compatible CPUs
  183. * such as the S3C2440 and S3C2442.
  184. *
  185. * We cannot use a system device as we are needed before any
  186. * of the init-calls that initialise the devices are actually
  187. * done.
  188. */
  189. int __init s3c2410_baseclk_add(void)
  190. {
  191. unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
  192. unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
  193. struct clk *clkp;
  194. struct clk *xtal;
  195. int ret;
  196. int ptr;
  197. clk_upll.enable = s3c2410_upll_enable;
  198. if (s3c24xx_register_clock(&clk_usb_bus) < 0)
  199. printk(KERN_ERR "failed to register usb bus clock\n");
  200. /* register clocks from clock array */
  201. clkp = init_clocks;
  202. for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
  203. /* ensure that we note the clock state */
  204. clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
  205. ret = s3c24xx_register_clock(clkp);
  206. if (ret < 0) {
  207. printk(KERN_ERR "Failed to register clock %s (%d)\n",
  208. clkp->name, ret);
  209. }
  210. }
  211. /* We must be careful disabling the clocks we are not intending to
  212. * be using at boot time, as subsytems such as the LCD which do
  213. * their own DMA requests to the bus can cause the system to lockup
  214. * if they where in the middle of requesting bus access.
  215. *
  216. * Disabling the LCD clock if the LCD is active is very dangerous,
  217. * and therefore the bootloader should be careful to not enable
  218. * the LCD clock if it is not needed.
  219. */
  220. /* install (and disable) the clocks we do not need immediately */
  221. clkp = init_clocks_disable;
  222. for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
  223. ret = s3c24xx_register_clock(clkp);
  224. if (ret < 0) {
  225. printk(KERN_ERR "Failed to register clock %s (%d)\n",
  226. clkp->name, ret);
  227. }
  228. s3c2410_clkcon_enable(clkp, 0);
  229. }
  230. /* show the clock-slow value */
  231. xtal = clk_get(NULL, "xtal");
  232. printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
  233. print_mhz(clk_get_rate(xtal) /
  234. ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
  235. (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
  236. (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
  237. (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
  238. return 0;
  239. }