sleep.S 4.8 KB

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  1. /*
  2. * linux/arch/arm/mach-pnx4008/sleep.S
  3. *
  4. * PNX4008 support for STOP mode and SDRAM self-refresh
  5. *
  6. * Authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
  7. *
  8. * 2005 (c) MontaVista Software, Inc. This file is licensed under
  9. * the terms of the GNU General Public License version 2. This program
  10. * is licensed "as is" without any warranty of any kind, whether express
  11. * or implied.
  12. */
  13. #include <linux/linkage.h>
  14. #include <asm/assembler.h>
  15. #include <asm/hardware.h>
  16. #define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
  17. #define PWR_CTRL_REG_OFFS 0x44
  18. #define SDRAM_CFG_VA_BASE IO_ADDRESS(PNX4008_SDRAM_CFG_BASE)
  19. #define MPMC_STATUS_REG_OFFS 0x4
  20. .text
  21. ENTRY(pnx4008_cpu_suspend)
  22. @this function should be entered in Direct run mode.
  23. @ save registers on stack
  24. stmfd sp!, {r0 - r6, lr}
  25. @ setup Power Manager base address in r4
  26. @ and put it's value in r5
  27. mov r4, #(PWRMAN_VA_BASE & 0xff000000)
  28. orr r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
  29. orr r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
  30. orr r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
  31. ldr r5, [r4, #PWR_CTRL_REG_OFFS]
  32. @ setup SDRAM controller base address in r2
  33. @ and put it's value in r3
  34. mov r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
  35. orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
  36. orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
  37. orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
  38. ldr r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
  39. @ clear SDRAM self-refresh bit latch
  40. and r5, r5, #(~(1 << 8))
  41. @ clear SDRAM self-refresh bit
  42. and r5, r5, #(~(1 << 9))
  43. str r5, [r4, #PWR_CTRL_REG_OFFS]
  44. @ do save current bit settings in r1
  45. mov r1, r5
  46. @ set SDRAM self-refresh bit
  47. orr r5, r5, #(1 << 9)
  48. str r5, [r4, #PWR_CTRL_REG_OFFS]
  49. @ set SDRAM self-refresh bit latch
  50. orr r5, r5, #(1 << 8)
  51. str r5, [r4, #PWR_CTRL_REG_OFFS]
  52. @ clear SDRAM self-refresh bit latch
  53. and r5, r5, #(~(1 << 8))
  54. str r5, [r4, #PWR_CTRL_REG_OFFS]
  55. @ clear SDRAM self-refresh bit
  56. and r5, r5, #(~(1 << 9))
  57. str r5, [r4, #PWR_CTRL_REG_OFFS]
  58. @ wait for SDRAM to get into self-refresh mode
  59. 2: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
  60. tst r3, #(1 << 2)
  61. beq 2b
  62. @ to prepare SDRAM to get out of self-refresh mode after wakeup
  63. orr r5, r5, #(1 << 7)
  64. str r5, [r4, #PWR_CTRL_REG_OFFS]
  65. @ do enter stop mode
  66. orr r5, r5, #(1 << 0)
  67. str r5, [r4, #PWR_CTRL_REG_OFFS]
  68. nop
  69. nop
  70. nop
  71. nop
  72. nop
  73. nop
  74. nop
  75. nop
  76. nop
  77. @ sleeping now...
  78. @ coming out of STOP mode into Direct Run mode
  79. @ clear STOP mode and SDRAM self-refresh bits
  80. str r1, [r4, #PWR_CTRL_REG_OFFS]
  81. @ wait for SDRAM to get out self-refresh mode
  82. 3: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
  83. tst r3, #5
  84. bne 3b
  85. @ restore regs and return
  86. ldmfd sp!, {r0 - r6, pc}
  87. ENTRY(pnx4008_cpu_suspend_sz)
  88. .word . - pnx4008_cpu_suspend
  89. ENTRY(pnx4008_cpu_standby)
  90. @ save registers on stack
  91. stmfd sp!, {r0 - r6, lr}
  92. @ setup Power Manager base address in r4
  93. @ and put it's value in r5
  94. mov r4, #(PWRMAN_VA_BASE & 0xff000000)
  95. orr r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
  96. orr r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
  97. orr r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
  98. ldr r5, [r4, #PWR_CTRL_REG_OFFS]
  99. @ setup SDRAM controller base address in r2
  100. @ and put it's value in r3
  101. mov r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
  102. orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
  103. orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
  104. orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
  105. ldr r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
  106. @ clear SDRAM self-refresh bit latch
  107. and r5, r5, #(~(1 << 8))
  108. @ clear SDRAM self-refresh bit
  109. and r5, r5, #(~(1 << 9))
  110. str r5, [r4, #PWR_CTRL_REG_OFFS]
  111. @ do save current bit settings in r1
  112. mov r1, r5
  113. @ set SDRAM self-refresh bit
  114. orr r5, r5, #(1 << 9)
  115. str r5, [r4, #PWR_CTRL_REG_OFFS]
  116. @ set SDRAM self-refresh bit latch
  117. orr r5, r5, #(1 << 8)
  118. str r5, [r4, #PWR_CTRL_REG_OFFS]
  119. @ clear SDRAM self-refresh bit latch
  120. and r5, r5, #(~(1 << 8))
  121. str r5, [r4, #PWR_CTRL_REG_OFFS]
  122. @ clear SDRAM self-refresh bit
  123. and r5, r5, #(~(1 << 9))
  124. str r5, [r4, #PWR_CTRL_REG_OFFS]
  125. @ wait for SDRAM to get into self-refresh mode
  126. 2: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
  127. tst r3, #(1 << 2)
  128. beq 2b
  129. @ set 'get out of self-refresh mode after wakeup' bit
  130. orr r5, r5, #(1 << 7)
  131. str r5, [r4, #PWR_CTRL_REG_OFFS]
  132. mcr p15, 0, r0, c7, c0, 4 @ kinda sleeping now...
  133. @ set SDRAM self-refresh bit latch
  134. orr r5, r5, #(1 << 8)
  135. str r5, [r4, #PWR_CTRL_REG_OFFS]
  136. @ clear SDRAM self-refresh bit latch
  137. and r5, r5, #(~(1 << 8))
  138. str r5, [r4, #PWR_CTRL_REG_OFFS]
  139. @ wait for SDRAM to get out self-refresh mode
  140. 3: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
  141. tst r3, #5
  142. bne 3b
  143. @ restore regs and return
  144. ldmfd sp!, {r0 - r6, pc}
  145. ENTRY(pnx4008_cpu_standby_sz)
  146. .word . - pnx4008_cpu_standby
  147. ENTRY(pnx4008_cache_clean_invalidate)
  148. stmfd sp!, {r0 - r6, lr}
  149. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  150. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  151. #else
  152. 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
  153. bne 1b
  154. #endif
  155. ldmfd sp!, {r0 - r6, pc}