irq.c 3.7 KB

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  1. /*
  2. * arch/arm/mach-pnx4008/irq.c
  3. *
  4. * PNX4008 IRQ controller driver
  5. *
  6. * Author: Dmitry Chigirev <source@mvista.com>
  7. *
  8. * Based on reference code received from Philips:
  9. * Copyright (C) 2003 Philips Semiconductors
  10. *
  11. * 2005 (c) MontaVista Software, Inc. This file is licensed under
  12. * the terms of the GNU General Public License version 2. This program
  13. * is licensed "as is" without any warranty of any kind, whether express
  14. * or implied.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/types.h>
  18. #include <linux/mm.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/list.h>
  21. #include <linux/init.h>
  22. #include <linux/ioport.h>
  23. #include <linux/device.h>
  24. #include <linux/irq.h>
  25. #include <asm/hardware.h>
  26. #include <asm/io.h>
  27. #include <asm/setup.h>
  28. #include <asm/mach-types.h>
  29. #include <asm/pgtable.h>
  30. #include <asm/page.h>
  31. #include <asm/system.h>
  32. #include <asm/mach/arch.h>
  33. #include <asm/mach/irq.h>
  34. #include <asm/mach/map.h>
  35. #include <asm/arch/irq.h>
  36. static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
  37. static void pnx4008_mask_irq(unsigned int irq)
  38. {
  39. __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
  40. }
  41. static void pnx4008_unmask_irq(unsigned int irq)
  42. {
  43. __raw_writel(__raw_readl(INTC_ER(irq)) | INTC_BIT(irq), INTC_ER(irq)); /* unmask interrupt */
  44. }
  45. static void pnx4008_mask_ack_irq(unsigned int irq)
  46. {
  47. __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
  48. __raw_writel(INTC_BIT(irq), INTC_SR(irq)); /* clear interrupt status */
  49. }
  50. static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
  51. {
  52. switch (type) {
  53. case IRQT_RISING:
  54. __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
  55. __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */
  56. set_irq_handler(irq, handle_edge_irq);
  57. break;
  58. case IRQT_FALLING:
  59. __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
  60. __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */
  61. set_irq_handler(irq, handle_edge_irq);
  62. break;
  63. case IRQT_LOW:
  64. __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
  65. __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */
  66. set_irq_handler(irq, handle_level_irq);
  67. break;
  68. case IRQT_HIGH:
  69. __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
  70. __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */
  71. set_irq_handler(irq, handle_level_irq);
  72. break;
  73. /* IRQT_BOTHEDGE is not supported */
  74. default:
  75. printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
  76. return -1;
  77. }
  78. return 0;
  79. }
  80. static struct irq_chip pnx4008_irq_chip = {
  81. .ack = pnx4008_mask_ack_irq,
  82. .mask = pnx4008_mask_irq,
  83. .unmask = pnx4008_unmask_irq,
  84. .set_type = pnx4008_set_irq_type,
  85. };
  86. void __init pnx4008_init_irq(void)
  87. {
  88. unsigned int i;
  89. /* configure IRQ's */
  90. for (i = 0; i < NR_IRQS; i++) {
  91. set_irq_flags(i, IRQF_VALID);
  92. set_irq_chip(i, &pnx4008_irq_chip);
  93. pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
  94. }
  95. /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
  96. pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]);
  97. pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]);
  98. pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]);
  99. pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]);
  100. /* mask all others */
  101. __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
  102. (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
  103. INTC_ER(MAIN_BASE_INT));
  104. __raw_writel(0, INTC_ER(SIC1_BASE_INT));
  105. __raw_writel(0, INTC_ER(SIC2_BASE_INT));
  106. }