clock.c 20 KB

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  1. /*
  2. * arch/arm/mach-pnx4008/clock.c
  3. *
  4. * Clock control driver for PNX4008
  5. *
  6. * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
  7. * Generic clock management functions are partially based on:
  8. * linux/arch/arm/mach-omap/clock.c
  9. *
  10. * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
  11. * the terms of the GNU General Public License version 2. This program
  12. * is licensed "as is" without any warranty of any kind, whether express
  13. * or implied.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/list.h>
  18. #include <linux/errno.h>
  19. #include <linux/device.h>
  20. #include <linux/err.h>
  21. #include <linux/delay.h>
  22. #include <asm/semaphore.h>
  23. #include <asm/hardware.h>
  24. #include <asm/io.h>
  25. #include <asm/arch/clock.h>
  26. #include "clock.h"
  27. /*forward declaration*/
  28. static struct clk per_ck;
  29. static struct clk hclk_ck;
  30. static struct clk ck_1MHz;
  31. static struct clk ck_13MHz;
  32. static struct clk ck_pll1;
  33. static int local_set_rate(struct clk *clk, u32 rate);
  34. static inline void clock_lock(void)
  35. {
  36. local_irq_disable();
  37. }
  38. static inline void clock_unlock(void)
  39. {
  40. local_irq_enable();
  41. }
  42. static void propagate_rate(struct clk *clk)
  43. {
  44. struct clk *tmp_clk;
  45. tmp_clk = clk;
  46. while (tmp_clk->propagate_next) {
  47. tmp_clk = tmp_clk->propagate_next;
  48. local_set_rate(tmp_clk, tmp_clk->user_rate);
  49. }
  50. }
  51. static inline void clk_reg_disable(struct clk *clk)
  52. {
  53. if (clk->enable_reg)
  54. __raw_writel(__raw_readl(clk->enable_reg) &
  55. ~(1 << clk->enable_shift), clk->enable_reg);
  56. }
  57. static inline void clk_reg_enable(struct clk *clk)
  58. {
  59. if (clk->enable_reg)
  60. __raw_writel(__raw_readl(clk->enable_reg) |
  61. (1 << clk->enable_shift), clk->enable_reg);
  62. }
  63. static inline void clk_reg_disable1(struct clk *clk)
  64. {
  65. if (clk->enable_reg1)
  66. __raw_writel(__raw_readl(clk->enable_reg1) &
  67. ~(1 << clk->enable_shift1), clk->enable_reg1);
  68. }
  69. static inline void clk_reg_enable1(struct clk *clk)
  70. {
  71. if (clk->enable_reg1)
  72. __raw_writel(__raw_readl(clk->enable_reg1) |
  73. (1 << clk->enable_shift1), clk->enable_reg1);
  74. }
  75. static int clk_wait_for_pll_lock(struct clk *clk)
  76. {
  77. int i;
  78. i = 0;
  79. while (i++ < 0xFFF && !(__raw_readl(clk->scale_reg) & 1)) ; /*wait for PLL to lock */
  80. if (!(__raw_readl(clk->scale_reg) & 1)) {
  81. printk(KERN_ERR
  82. "%s ERROR: failed to lock, scale reg data: %x\n",
  83. clk->name, __raw_readl(clk->scale_reg));
  84. return -1;
  85. }
  86. return 0;
  87. }
  88. static int switch_to_dirty_13mhz(struct clk *clk)
  89. {
  90. int i;
  91. int ret;
  92. u32 tmp_reg;
  93. ret = 0;
  94. if (!clk->rate)
  95. clk_reg_enable1(clk);
  96. tmp_reg = __raw_readl(clk->parent_switch_reg);
  97. /*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */
  98. if (!(tmp_reg & 1)) {
  99. tmp_reg |= (1 << 1); /* Trigger switch to 13'MHz (dirty) clock */
  100. __raw_writel(tmp_reg, clk->parent_switch_reg);
  101. i = 0;
  102. while (i++ < 0xFFF && !(__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13'MHz selection status */
  103. if (!(__raw_readl(clk->parent_switch_reg) & 1)) {
  104. printk(KERN_ERR
  105. "%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n",
  106. clk->name, __raw_readl(clk->parent_switch_reg));
  107. ret = -1;
  108. }
  109. }
  110. if (!clk->rate)
  111. clk_reg_disable1(clk);
  112. return ret;
  113. }
  114. static int switch_to_clean_13mhz(struct clk *clk)
  115. {
  116. int i;
  117. int ret;
  118. u32 tmp_reg;
  119. ret = 0;
  120. if (!clk->rate)
  121. clk_reg_enable1(clk);
  122. tmp_reg = __raw_readl(clk->parent_switch_reg);
  123. /*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */
  124. if (tmp_reg & 1) {
  125. tmp_reg &= ~(1 << 1); /* Trigger switch to 13MHz (clean) clock */
  126. __raw_writel(tmp_reg, clk->parent_switch_reg);
  127. i = 0;
  128. while (i++ < 0xFFF && (__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13MHz selection status */
  129. if (__raw_readl(clk->parent_switch_reg) & 1) {
  130. printk(KERN_ERR
  131. "%s ERROR: failed to select 13MHz, parent sw reg data: %x\n",
  132. clk->name, __raw_readl(clk->parent_switch_reg));
  133. ret = -1;
  134. }
  135. }
  136. if (!clk->rate)
  137. clk_reg_disable1(clk);
  138. return ret;
  139. }
  140. static int set_13MHz_parent(struct clk *clk, struct clk *parent)
  141. {
  142. int ret = -EINVAL;
  143. if (parent == &ck_13MHz)
  144. ret = switch_to_clean_13mhz(clk);
  145. else if (parent == &ck_pll1)
  146. ret = switch_to_dirty_13mhz(clk);
  147. return ret;
  148. }
  149. #define PLL160_MIN_FCCO 156000
  150. #define PLL160_MAX_FCCO 320000
  151. /*
  152. * Calculate pll160 settings.
  153. * Possible input: up to 320MHz with step of clk->parent->rate.
  154. * In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
  155. * Ignored paths: "feedback" (bit 13 set), "div-by-N".
  156. * Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
  157. * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
  158. * Please refer to PNX4008 IC manual for details.
  159. */
  160. static int pll160_set_rate(struct clk *clk, u32 rate)
  161. {
  162. u32 tmp_reg, tmp_m, tmp_2p, i;
  163. u32 parent_rate;
  164. int ret = -EINVAL;
  165. parent_rate = clk->parent->rate;
  166. if (!parent_rate)
  167. goto out;
  168. /* set direct run for ARM or disable output for others */
  169. clk_reg_disable(clk);
  170. /* disable source input as well (ignored for ARM) */
  171. clk_reg_disable1(clk);
  172. tmp_reg = __raw_readl(clk->scale_reg);
  173. tmp_reg &= ~0x1ffff; /*clear all settings, power down */
  174. __raw_writel(tmp_reg, clk->scale_reg);
  175. rate -= rate % parent_rate; /*round down the input */
  176. if (rate > PLL160_MAX_FCCO)
  177. rate = PLL160_MAX_FCCO;
  178. if (!rate) {
  179. clk->rate = 0;
  180. ret = 0;
  181. goto out;
  182. }
  183. clk_reg_enable1(clk);
  184. tmp_reg = __raw_readl(clk->scale_reg);
  185. if (rate == parent_rate) {
  186. /*enter direct bypass mode */
  187. tmp_reg |= ((1 << 14) | (1 << 15));
  188. __raw_writel(tmp_reg, clk->scale_reg);
  189. clk->rate = parent_rate;
  190. clk_reg_enable(clk);
  191. ret = 0;
  192. goto out;
  193. }
  194. i = 0;
  195. for (tmp_2p = 1; tmp_2p < 16; tmp_2p <<= 1) {
  196. if (rate * tmp_2p >= PLL160_MIN_FCCO)
  197. break;
  198. i++;
  199. }
  200. if (tmp_2p > 1)
  201. tmp_reg |= ((i - 1) << 11);
  202. else
  203. tmp_reg |= (1 << 14); /*direct mode, no divide */
  204. tmp_m = rate * tmp_2p;
  205. tmp_m /= parent_rate;
  206. tmp_reg |= (tmp_m - 1) << 1; /*calculate M */
  207. tmp_reg |= (1 << 16); /*power up PLL */
  208. __raw_writel(tmp_reg, clk->scale_reg);
  209. if (clk_wait_for_pll_lock(clk) < 0) {
  210. clk_reg_disable(clk);
  211. clk_reg_disable1(clk);
  212. tmp_reg = __raw_readl(clk->scale_reg);
  213. tmp_reg &= ~0x1ffff; /*clear all settings, power down */
  214. __raw_writel(tmp_reg, clk->scale_reg);
  215. clk->rate = 0;
  216. ret = -EFAULT;
  217. goto out;
  218. }
  219. clk->rate = (tmp_m * parent_rate) / tmp_2p;
  220. if (clk->flags & RATE_PROPAGATES)
  221. propagate_rate(clk);
  222. clk_reg_enable(clk);
  223. ret = 0;
  224. out:
  225. return ret;
  226. }
  227. /*configure PER_CLK*/
  228. static int per_clk_set_rate(struct clk *clk, u32 rate)
  229. {
  230. u32 tmp;
  231. tmp = __raw_readl(clk->scale_reg);
  232. tmp &= ~(0x1f << 2);
  233. tmp |= ((clk->parent->rate / clk->rate) - 1) << 2;
  234. __raw_writel(tmp, clk->scale_reg);
  235. clk->rate = rate;
  236. return 0;
  237. }
  238. /*configure HCLK*/
  239. static int hclk_set_rate(struct clk *clk, u32 rate)
  240. {
  241. u32 tmp;
  242. tmp = __raw_readl(clk->scale_reg);
  243. tmp = tmp & ~0x3;
  244. switch (rate) {
  245. case 1:
  246. break;
  247. case 2:
  248. tmp |= 1;
  249. break;
  250. case 4:
  251. tmp |= 2;
  252. break;
  253. }
  254. __raw_writel(tmp, clk->scale_reg);
  255. clk->rate = rate;
  256. return 0;
  257. }
  258. static u32 hclk_round_rate(struct clk *clk, u32 rate)
  259. {
  260. switch (rate) {
  261. case 1:
  262. case 4:
  263. return rate;
  264. }
  265. return 2;
  266. }
  267. static u32 per_clk_round_rate(struct clk *clk, u32 rate)
  268. {
  269. return CLK_RATE_13MHZ;
  270. }
  271. static int on_off_set_rate(struct clk *clk, u32 rate)
  272. {
  273. if (rate) {
  274. clk_reg_enable(clk);
  275. clk->rate = 1;
  276. } else {
  277. clk_reg_disable(clk);
  278. clk->rate = 0;
  279. }
  280. return 0;
  281. }
  282. static int on_off_inv_set_rate(struct clk *clk, u32 rate)
  283. {
  284. if (rate) {
  285. clk_reg_disable(clk); /*enable bit is inverted */
  286. clk->rate = 1;
  287. } else {
  288. clk_reg_enable(clk);
  289. clk->rate = 0;
  290. }
  291. return 0;
  292. }
  293. static u32 on_off_round_rate(struct clk *clk, u32 rate)
  294. {
  295. return (rate ? 1 : 0);
  296. }
  297. static u32 pll4_round_rate(struct clk *clk, u32 rate)
  298. {
  299. if (rate > CLK_RATE_208MHZ)
  300. rate = CLK_RATE_208MHZ;
  301. if (rate == CLK_RATE_208MHZ && hclk_ck.user_rate == 1)
  302. rate = CLK_RATE_208MHZ - CLK_RATE_13MHZ;
  303. return (rate - (rate % (hclk_ck.user_rate * CLK_RATE_13MHZ)));
  304. }
  305. static u32 pll3_round_rate(struct clk *clk, u32 rate)
  306. {
  307. if (rate > CLK_RATE_208MHZ)
  308. rate = CLK_RATE_208MHZ;
  309. return (rate - rate % CLK_RATE_13MHZ);
  310. }
  311. static u32 pll5_round_rate(struct clk *clk, u32 rate)
  312. {
  313. return (rate ? CLK_RATE_48MHZ : 0);
  314. }
  315. static u32 ck_13MHz_round_rate(struct clk *clk, u32 rate)
  316. {
  317. return (rate ? CLK_RATE_13MHZ : 0);
  318. }
  319. static int ck_13MHz_set_rate(struct clk *clk, u32 rate)
  320. {
  321. if (rate) {
  322. clk_reg_disable(clk); /*enable bit is inverted */
  323. udelay(500);
  324. clk->rate = CLK_RATE_13MHZ;
  325. ck_1MHz.rate = CLK_RATE_1MHZ;
  326. } else {
  327. clk_reg_enable(clk);
  328. clk->rate = 0;
  329. ck_1MHz.rate = 0;
  330. }
  331. return 0;
  332. }
  333. static int pll1_set_rate(struct clk *clk, u32 rate)
  334. {
  335. #if 0 /* doesn't work on some boards, probably a HW BUG */
  336. if (rate) {
  337. clk_reg_disable(clk); /*enable bit is inverted */
  338. if (!clk_wait_for_pll_lock(clk)) {
  339. clk->rate = CLK_RATE_13MHZ;
  340. } else {
  341. clk_reg_enable(clk);
  342. clk->rate = 0;
  343. }
  344. } else {
  345. clk_reg_enable(clk);
  346. clk->rate = 0;
  347. }
  348. #endif
  349. return 0;
  350. }
  351. /* Clock sources */
  352. static struct clk osc_13MHz = {
  353. .name = "osc_13MHz",
  354. .flags = FIXED_RATE,
  355. .rate = CLK_RATE_13MHZ,
  356. };
  357. static struct clk ck_13MHz = {
  358. .name = "ck_13MHz",
  359. .parent = &osc_13MHz,
  360. .flags = NEEDS_INITIALIZATION,
  361. .round_rate = &ck_13MHz_round_rate,
  362. .set_rate = &ck_13MHz_set_rate,
  363. .enable_reg = OSC13CTRL_REG,
  364. .enable_shift = 0,
  365. .rate = CLK_RATE_13MHZ,
  366. };
  367. static struct clk osc_32KHz = {
  368. .name = "osc_32KHz",
  369. .flags = FIXED_RATE,
  370. .rate = CLK_RATE_32KHZ,
  371. };
  372. /*attached to PLL5*/
  373. static struct clk ck_1MHz = {
  374. .name = "ck_1MHz",
  375. .flags = FIXED_RATE | PARENT_SET_RATE,
  376. .parent = &ck_13MHz,
  377. };
  378. /* PLL1 (397) - provides 13' MHz clock */
  379. static struct clk ck_pll1 = {
  380. .name = "ck_pll1",
  381. .parent = &osc_32KHz,
  382. .flags = NEEDS_INITIALIZATION,
  383. .round_rate = &ck_13MHz_round_rate,
  384. .set_rate = &pll1_set_rate,
  385. .enable_reg = PLLCTRL_REG,
  386. .enable_shift = 1,
  387. .scale_reg = PLLCTRL_REG,
  388. .rate = CLK_RATE_13MHZ,
  389. };
  390. /* CPU/Bus PLL */
  391. static struct clk ck_pll4 = {
  392. .name = "ck_pll4",
  393. .parent = &ck_pll1,
  394. .flags = RATE_PROPAGATES | NEEDS_INITIALIZATION,
  395. .propagate_next = &per_ck,
  396. .round_rate = &pll4_round_rate,
  397. .set_rate = &pll160_set_rate,
  398. .rate = CLK_RATE_208MHZ,
  399. .scale_reg = HCLKPLLCTRL_REG,
  400. .enable_reg = PWRCTRL_REG,
  401. .enable_shift = 2,
  402. .parent_switch_reg = SYSCLKCTRL_REG,
  403. .set_parent = &set_13MHz_parent,
  404. };
  405. /* USB PLL */
  406. static struct clk ck_pll5 = {
  407. .name = "ck_pll5",
  408. .parent = &ck_1MHz,
  409. .flags = NEEDS_INITIALIZATION,
  410. .round_rate = &pll5_round_rate,
  411. .set_rate = &pll160_set_rate,
  412. .scale_reg = USBCTRL_REG,
  413. .enable_reg = USBCTRL_REG,
  414. .enable_shift = 18,
  415. .enable_reg1 = USBCTRL_REG,
  416. .enable_shift1 = 17,
  417. };
  418. /* XPERTTeak DSP PLL */
  419. static struct clk ck_pll3 = {
  420. .name = "ck_pll3",
  421. .parent = &ck_pll1,
  422. .flags = NEEDS_INITIALIZATION,
  423. .round_rate = &pll3_round_rate,
  424. .set_rate = &pll160_set_rate,
  425. .scale_reg = DSPPLLCTRL_REG,
  426. .enable_reg = DSPCLKCTRL_REG,
  427. .enable_shift = 3,
  428. .enable_reg1 = DSPCLKCTRL_REG,
  429. .enable_shift1 = 2,
  430. .parent_switch_reg = DSPCLKCTRL_REG,
  431. .set_parent = &set_13MHz_parent,
  432. };
  433. static struct clk hclk_ck = {
  434. .name = "hclk_ck",
  435. .parent = &ck_pll4,
  436. .flags = PARENT_SET_RATE,
  437. .set_rate = &hclk_set_rate,
  438. .round_rate = &hclk_round_rate,
  439. .scale_reg = HCLKDIVCTRL_REG,
  440. .rate = 2,
  441. .user_rate = 2,
  442. };
  443. static struct clk per_ck = {
  444. .name = "per_ck",
  445. .parent = &ck_pll4,
  446. .flags = FIXED_RATE,
  447. .propagate_next = &hclk_ck,
  448. .set_rate = &per_clk_set_rate,
  449. .round_rate = &per_clk_round_rate,
  450. .scale_reg = HCLKDIVCTRL_REG,
  451. .rate = CLK_RATE_13MHZ,
  452. .user_rate = CLK_RATE_13MHZ,
  453. };
  454. static struct clk m2hclk_ck = {
  455. .name = "m2hclk_ck",
  456. .parent = &hclk_ck,
  457. .flags = NEEDS_INITIALIZATION,
  458. .round_rate = &on_off_round_rate,
  459. .set_rate = &on_off_inv_set_rate,
  460. .rate = 1,
  461. .enable_shift = 6,
  462. .enable_reg = PWRCTRL_REG,
  463. };
  464. static struct clk vfp9_ck = {
  465. .name = "vfp9_ck",
  466. .parent = &ck_pll4,
  467. .flags = NEEDS_INITIALIZATION,
  468. .round_rate = &on_off_round_rate,
  469. .set_rate = &on_off_set_rate,
  470. .rate = 1,
  471. .enable_shift = 4,
  472. .enable_reg = VFP9CLKCTRL_REG,
  473. };
  474. static struct clk keyscan_ck = {
  475. .name = "keyscan_ck",
  476. .parent = &osc_32KHz,
  477. .flags = NEEDS_INITIALIZATION,
  478. .round_rate = &on_off_round_rate,
  479. .set_rate = &on_off_set_rate,
  480. .enable_shift = 0,
  481. .enable_reg = KEYCLKCTRL_REG,
  482. };
  483. static struct clk touch_ck = {
  484. .name = "touch_ck",
  485. .parent = &osc_32KHz,
  486. .flags = NEEDS_INITIALIZATION,
  487. .round_rate = &on_off_round_rate,
  488. .set_rate = &on_off_set_rate,
  489. .enable_shift = 0,
  490. .enable_reg = TSCLKCTRL_REG,
  491. };
  492. static struct clk pwm1_ck = {
  493. .name = "pwm1_ck",
  494. .parent = &osc_32KHz,
  495. .flags = NEEDS_INITIALIZATION,
  496. .round_rate = &on_off_round_rate,
  497. .set_rate = &on_off_set_rate,
  498. .enable_shift = 0,
  499. .enable_reg = PWMCLKCTRL_REG,
  500. };
  501. static struct clk pwm2_ck = {
  502. .name = "pwm2_ck",
  503. .parent = &osc_32KHz,
  504. .flags = NEEDS_INITIALIZATION,
  505. .round_rate = &on_off_round_rate,
  506. .set_rate = &on_off_set_rate,
  507. .enable_shift = 2,
  508. .enable_reg = PWMCLKCTRL_REG,
  509. };
  510. static struct clk jpeg_ck = {
  511. .name = "jpeg_ck",
  512. .parent = &hclk_ck,
  513. .flags = NEEDS_INITIALIZATION,
  514. .round_rate = &on_off_round_rate,
  515. .set_rate = &on_off_set_rate,
  516. .enable_shift = 0,
  517. .enable_reg = JPEGCLKCTRL_REG,
  518. };
  519. static struct clk ms_ck = {
  520. .name = "ms_ck",
  521. .parent = &ck_pll4,
  522. .flags = NEEDS_INITIALIZATION,
  523. .round_rate = &on_off_round_rate,
  524. .set_rate = &on_off_set_rate,
  525. .enable_shift = 5,
  526. .enable_reg = MSCTRL_REG,
  527. };
  528. static struct clk dum_ck = {
  529. .name = "dum_ck",
  530. .parent = &hclk_ck,
  531. .flags = NEEDS_INITIALIZATION,
  532. .round_rate = &on_off_round_rate,
  533. .set_rate = &on_off_set_rate,
  534. .enable_shift = 0,
  535. .enable_reg = DUMCLKCTRL_REG,
  536. };
  537. static struct clk flash_ck = {
  538. .name = "flash_ck",
  539. .parent = &hclk_ck,
  540. .round_rate = &on_off_round_rate,
  541. .set_rate = &on_off_set_rate,
  542. .enable_shift = 1, /* Only MLC clock supported */
  543. .enable_reg = FLASHCLKCTRL_REG,
  544. };
  545. static struct clk i2c0_ck = {
  546. .name = "i2c0_ck",
  547. .parent = &per_ck,
  548. .flags = NEEDS_INITIALIZATION,
  549. .round_rate = &on_off_round_rate,
  550. .set_rate = &on_off_set_rate,
  551. .enable_shift = 0,
  552. .enable_reg = I2CCLKCTRL_REG,
  553. };
  554. static struct clk i2c1_ck = {
  555. .name = "i2c1_ck",
  556. .parent = &per_ck,
  557. .flags = NEEDS_INITIALIZATION,
  558. .round_rate = &on_off_round_rate,
  559. .set_rate = &on_off_set_rate,
  560. .enable_shift = 1,
  561. .enable_reg = I2CCLKCTRL_REG,
  562. };
  563. static struct clk i2c2_ck = {
  564. .name = "i2c2_ck",
  565. .parent = &per_ck,
  566. .flags = NEEDS_INITIALIZATION,
  567. .round_rate = &on_off_round_rate,
  568. .set_rate = &on_off_set_rate,
  569. .enable_shift = 2,
  570. .enable_reg = USB_OTG_CLKCTRL_REG,
  571. };
  572. static struct clk spi0_ck = {
  573. .name = "spi0_ck",
  574. .parent = &hclk_ck,
  575. .flags = NEEDS_INITIALIZATION,
  576. .round_rate = &on_off_round_rate,
  577. .set_rate = &on_off_set_rate,
  578. .enable_shift = 0,
  579. .enable_reg = SPICTRL_REG,
  580. };
  581. static struct clk spi1_ck = {
  582. .name = "spi1_ck",
  583. .parent = &hclk_ck,
  584. .flags = NEEDS_INITIALIZATION,
  585. .round_rate = &on_off_round_rate,
  586. .set_rate = &on_off_set_rate,
  587. .enable_shift = 4,
  588. .enable_reg = SPICTRL_REG,
  589. };
  590. static struct clk dma_ck = {
  591. .name = "dma_ck",
  592. .parent = &hclk_ck,
  593. .round_rate = &on_off_round_rate,
  594. .set_rate = &on_off_set_rate,
  595. .enable_shift = 0,
  596. .enable_reg = DMACLKCTRL_REG,
  597. };
  598. static struct clk uart3_ck = {
  599. .name = "uart3_ck",
  600. .parent = &per_ck,
  601. .flags = NEEDS_INITIALIZATION,
  602. .round_rate = &on_off_round_rate,
  603. .set_rate = &on_off_set_rate,
  604. .rate = 1,
  605. .enable_shift = 0,
  606. .enable_reg = UARTCLKCTRL_REG,
  607. };
  608. static struct clk uart4_ck = {
  609. .name = "uart4_ck",
  610. .parent = &per_ck,
  611. .flags = NEEDS_INITIALIZATION,
  612. .round_rate = &on_off_round_rate,
  613. .set_rate = &on_off_set_rate,
  614. .enable_shift = 1,
  615. .enable_reg = UARTCLKCTRL_REG,
  616. };
  617. static struct clk uart5_ck = {
  618. .name = "uart5_ck",
  619. .parent = &per_ck,
  620. .flags = NEEDS_INITIALIZATION,
  621. .round_rate = &on_off_round_rate,
  622. .set_rate = &on_off_set_rate,
  623. .rate = 1,
  624. .enable_shift = 2,
  625. .enable_reg = UARTCLKCTRL_REG,
  626. };
  627. static struct clk uart6_ck = {
  628. .name = "uart6_ck",
  629. .parent = &per_ck,
  630. .flags = NEEDS_INITIALIZATION,
  631. .round_rate = &on_off_round_rate,
  632. .set_rate = &on_off_set_rate,
  633. .enable_shift = 3,
  634. .enable_reg = UARTCLKCTRL_REG,
  635. };
  636. static struct clk wdt_ck = {
  637. .name = "wdt_ck",
  638. .parent = &per_ck,
  639. .flags = NEEDS_INITIALIZATION,
  640. .round_rate = &on_off_round_rate,
  641. .set_rate = &on_off_set_rate,
  642. .enable_shift = 0,
  643. .enable_reg = TIMCLKCTRL_REG,
  644. };
  645. /* These clocks are visible outside this module
  646. * and can be initialized
  647. */
  648. static struct clk *onchip_clks[] = {
  649. &ck_13MHz,
  650. &ck_pll1,
  651. &ck_pll4,
  652. &ck_pll5,
  653. &ck_pll3,
  654. &vfp9_ck,
  655. &m2hclk_ck,
  656. &hclk_ck,
  657. &dma_ck,
  658. &flash_ck,
  659. &dum_ck,
  660. &keyscan_ck,
  661. &pwm1_ck,
  662. &pwm2_ck,
  663. &jpeg_ck,
  664. &ms_ck,
  665. &touch_ck,
  666. &i2c0_ck,
  667. &i2c1_ck,
  668. &i2c2_ck,
  669. &spi0_ck,
  670. &spi1_ck,
  671. &uart3_ck,
  672. &uart4_ck,
  673. &uart5_ck,
  674. &uart6_ck,
  675. &wdt_ck,
  676. };
  677. static int local_clk_enable(struct clk *clk)
  678. {
  679. int ret = 0;
  680. if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
  681. && clk->user_rate)
  682. ret = clk->set_rate(clk, clk->user_rate);
  683. return ret;
  684. }
  685. static void local_clk_disable(struct clk *clk)
  686. {
  687. if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
  688. clk->set_rate(clk, 0);
  689. }
  690. static void local_clk_unuse(struct clk *clk)
  691. {
  692. if (clk->usecount > 0 && !(--clk->usecount)) {
  693. local_clk_disable(clk);
  694. if (clk->parent)
  695. local_clk_unuse(clk->parent);
  696. }
  697. }
  698. static int local_clk_use(struct clk *clk)
  699. {
  700. int ret = 0;
  701. if (clk->usecount++ == 0) {
  702. if (clk->parent)
  703. ret = local_clk_use(clk->parent);
  704. if (ret != 0) {
  705. clk->usecount--;
  706. goto out;
  707. }
  708. ret = local_clk_enable(clk);
  709. if (ret != 0 && clk->parent) {
  710. local_clk_unuse(clk->parent);
  711. clk->usecount--;
  712. }
  713. }
  714. out:
  715. return ret;
  716. }
  717. static int local_set_rate(struct clk *clk, u32 rate)
  718. {
  719. int ret = -EINVAL;
  720. if (clk->set_rate) {
  721. if (clk->user_rate == clk->rate && clk->parent->rate) {
  722. /* if clock enabled or rate not set */
  723. clk->user_rate = clk->round_rate(clk, rate);
  724. ret = clk->set_rate(clk, clk->user_rate);
  725. } else
  726. clk->user_rate = clk->round_rate(clk, rate);
  727. ret = 0;
  728. }
  729. return ret;
  730. }
  731. int clk_set_rate(struct clk *clk, unsigned long rate)
  732. {
  733. int ret = -EINVAL;
  734. if (clk->flags & FIXED_RATE)
  735. goto out;
  736. clock_lock();
  737. if ((clk->flags & PARENT_SET_RATE) && clk->parent) {
  738. clk->user_rate = clk->round_rate(clk, rate);
  739. /* parent clock needs to be refreshed
  740. for the setting to take effect */
  741. } else {
  742. ret = local_set_rate(clk, rate);
  743. }
  744. ret = 0;
  745. clock_unlock();
  746. out:
  747. return ret;
  748. }
  749. EXPORT_SYMBOL(clk_set_rate);
  750. struct clk *clk_get(struct device *dev, const char *id)
  751. {
  752. struct clk *clk = ERR_PTR(-ENOENT);
  753. struct clk **clkp;
  754. clock_lock();
  755. for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
  756. clkp++) {
  757. if (strcmp(id, (*clkp)->name) == 0
  758. && try_module_get((*clkp)->owner)) {
  759. clk = (*clkp);
  760. break;
  761. }
  762. }
  763. clock_unlock();
  764. return clk;
  765. }
  766. EXPORT_SYMBOL(clk_get);
  767. void clk_put(struct clk *clk)
  768. {
  769. clock_lock();
  770. if (clk && !IS_ERR(clk))
  771. module_put(clk->owner);
  772. clock_unlock();
  773. }
  774. EXPORT_SYMBOL(clk_put);
  775. unsigned long clk_get_rate(struct clk *clk)
  776. {
  777. unsigned long ret;
  778. clock_lock();
  779. ret = clk->rate;
  780. clock_unlock();
  781. return ret;
  782. }
  783. EXPORT_SYMBOL(clk_get_rate);
  784. int clk_enable(struct clk *clk)
  785. {
  786. int ret = 0;
  787. clock_lock();
  788. ret = local_clk_use(clk);
  789. clock_unlock();
  790. return ret;
  791. }
  792. EXPORT_SYMBOL(clk_enable);
  793. void clk_disable(struct clk *clk)
  794. {
  795. clock_lock();
  796. local_clk_unuse(clk);
  797. clock_unlock();
  798. }
  799. EXPORT_SYMBOL(clk_disable);
  800. long clk_round_rate(struct clk *clk, unsigned long rate)
  801. {
  802. long ret;
  803. clock_lock();
  804. if (clk->round_rate)
  805. ret = clk->round_rate(clk, rate);
  806. else
  807. ret = clk->rate;
  808. clock_unlock();
  809. return ret;
  810. }
  811. EXPORT_SYMBOL(clk_round_rate);
  812. int clk_set_parent(struct clk *clk, struct clk *parent)
  813. {
  814. int ret = -ENODEV;
  815. if (!clk->set_parent)
  816. goto out;
  817. clock_lock();
  818. ret = clk->set_parent(clk, parent);
  819. if (!ret)
  820. clk->parent = parent;
  821. clock_unlock();
  822. out:
  823. return ret;
  824. }
  825. EXPORT_SYMBOL(clk_set_parent);
  826. static int __init clk_init(void)
  827. {
  828. struct clk **clkp;
  829. /* Disable autoclocking, as it doesn't seem to work */
  830. __raw_writel(0xff, AUTOCLK_CTRL);
  831. for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
  832. clkp++) {
  833. if (((*clkp)->flags & NEEDS_INITIALIZATION)
  834. && ((*clkp)->set_rate)) {
  835. (*clkp)->user_rate = (*clkp)->rate;
  836. local_set_rate((*clkp), (*clkp)->user_rate);
  837. if ((*clkp)->set_parent)
  838. (*clkp)->set_parent((*clkp), (*clkp)->parent);
  839. }
  840. pr_debug("%s: clock %s, rate %ld\n",
  841. __FUNCTION__, (*clkp)->name, (*clkp)->rate);
  842. }
  843. local_clk_use(&ck_pll4);
  844. /* if ck_13MHz is not used, disable it. */
  845. if (ck_13MHz.usecount == 0)
  846. local_clk_disable(&ck_13MHz);
  847. /* Disable autoclocking */
  848. __raw_writeb(0xff, AUTOCLK_CTRL);
  849. return 0;
  850. }
  851. arch_initcall(clk_init);