board-a9m9750dev.c 4.9 KB

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  1. /*
  2. * arch/arm/mach-ns9xxx/board-a9m9750dev.c
  3. *
  4. * Copyright (C) 2006,2007 by Digi International Inc.
  5. * All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. */
  11. #include <linux/platform_device.h>
  12. #include <linux/serial_8250.h>
  13. #include <linux/irq.h>
  14. #include <asm/mach/map.h>
  15. #include <asm/arch-ns9xxx/board.h>
  16. #include <asm/arch-ns9xxx/regs-sys.h>
  17. #include <asm/arch-ns9xxx/regs-mem.h>
  18. #include <asm/arch-ns9xxx/regs-bbu.h>
  19. #include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
  20. #include "board-a9m9750dev.h"
  21. static struct map_desc board_a9m9750dev_io_desc[] __initdata = {
  22. { /* FPGA on CS0 */
  23. .virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)),
  24. .pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)),
  25. .length = NS9XXX_CS0STAT_LENGTH,
  26. .type = MT_DEVICE,
  27. },
  28. };
  29. void __init board_a9m9750dev_map_io(void)
  30. {
  31. iotable_init(board_a9m9750dev_io_desc,
  32. ARRAY_SIZE(board_a9m9750dev_io_desc));
  33. }
  34. static void a9m9750dev_fpga_ack_irq(unsigned int irq)
  35. {
  36. /* nothing */
  37. }
  38. static void a9m9750dev_fpga_mask_irq(unsigned int irq)
  39. {
  40. FPGA_IER &= ~(1 << (irq - FPGA_IRQ(0)));
  41. }
  42. static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
  43. {
  44. a9m9750dev_fpga_mask_irq(irq);
  45. a9m9750dev_fpga_ack_irq(irq);
  46. }
  47. static void a9m9750dev_fpga_unmask_irq(unsigned int irq)
  48. {
  49. FPGA_IER |= 1 << (irq - FPGA_IRQ(0));
  50. }
  51. static struct irq_chip a9m9750dev_fpga_chip = {
  52. .ack = a9m9750dev_fpga_ack_irq,
  53. .mask = a9m9750dev_fpga_mask_irq,
  54. .mask_ack = a9m9750dev_fpga_maskack_irq,
  55. .unmask = a9m9750dev_fpga_unmask_irq,
  56. };
  57. static void a9m9750dev_fpga_demux_handler(unsigned int irq,
  58. struct irq_desc *desc)
  59. {
  60. int stat = FPGA_ISR;
  61. while (stat != 0) {
  62. int irqno = fls(stat) - 1;
  63. stat &= ~(1 << irqno);
  64. desc = irq_desc + FPGA_IRQ(irqno);
  65. desc_handle_irq(irqno, desc);
  66. }
  67. }
  68. void __init board_a9m9750dev_init_irq(void)
  69. {
  70. u32 reg;
  71. int i;
  72. /*
  73. * configure gpio for IRQ_EXT2
  74. * use GPIO 11, because GPIO 32 is used for the LCD
  75. */
  76. /* XXX: proper GPIO handling */
  77. BBU_GC(2) &= ~0x2000;
  78. for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
  79. set_irq_chip(i, &a9m9750dev_fpga_chip);
  80. set_irq_handler(i, handle_level_irq);
  81. set_irq_flags(i, IRQF_VALID);
  82. }
  83. /* IRQ_EXT2: level sensitive + active low */
  84. reg = SYS_EIC(2);
  85. REGSET(reg, SYS_EIC, PLTY, AL);
  86. REGSET(reg, SYS_EIC, LVEDG, LEVEL);
  87. SYS_EIC(2) = reg;
  88. set_irq_chained_handler(IRQ_EXT2,
  89. a9m9750dev_fpga_demux_handler);
  90. }
  91. static struct plat_serial8250_port board_a9m9750dev_serial8250_port[] = {
  92. {
  93. .iobase = FPGA_UARTA_BASE,
  94. .membase = (unsigned char*)FPGA_UARTA_BASE,
  95. .mapbase = FPGA_UARTA_BASE,
  96. .irq = IRQ_FPGA_UARTA,
  97. .iotype = UPIO_MEM,
  98. .uartclk = 18432000,
  99. .regshift = 0,
  100. .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
  101. }, {
  102. .iobase = FPGA_UARTB_BASE,
  103. .membase = (unsigned char*)FPGA_UARTB_BASE,
  104. .mapbase = FPGA_UARTB_BASE,
  105. .irq = IRQ_FPGA_UARTB,
  106. .iotype = UPIO_MEM,
  107. .uartclk = 18432000,
  108. .regshift = 0,
  109. .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
  110. }, {
  111. .iobase = FPGA_UARTC_BASE,
  112. .membase = (unsigned char*)FPGA_UARTC_BASE,
  113. .mapbase = FPGA_UARTC_BASE,
  114. .irq = IRQ_FPGA_UARTC,
  115. .iotype = UPIO_MEM,
  116. .uartclk = 18432000,
  117. .regshift = 0,
  118. .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
  119. }, {
  120. .iobase = FPGA_UARTD_BASE,
  121. .membase = (unsigned char*)FPGA_UARTD_BASE,
  122. .mapbase = FPGA_UARTD_BASE,
  123. .irq = IRQ_FPGA_UARTD,
  124. .iotype = UPIO_MEM,
  125. .uartclk = 18432000,
  126. .regshift = 0,
  127. .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
  128. }, {
  129. /* end marker */
  130. },
  131. };
  132. static struct platform_device board_a9m9750dev_serial_device = {
  133. .name = "serial8250",
  134. .dev = {
  135. .platform_data = board_a9m9750dev_serial8250_port,
  136. },
  137. };
  138. static struct platform_device *board_a9m9750dev_devices[] __initdata = {
  139. &board_a9m9750dev_serial_device,
  140. };
  141. void __init board_a9m9750dev_init_machine(void)
  142. {
  143. u32 reg;
  144. /* setup static CS0: memory base ... */
  145. REGSETIM(SYS_SMCSSMB(0), SYS_SMCSSMB, CSxB,
  146. NS9XXX_CSxSTAT_PHYS(0) >> 12);
  147. /* ... and mask */
  148. reg = SYS_SMCSSMM(0);
  149. REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff);
  150. REGSET(reg, SYS_SMCSSMM, CSEx, EN);
  151. SYS_SMCSSMM(0) = reg;
  152. /* setup static CS0: memory configuration */
  153. reg = MEM_SMC(0);
  154. REGSET(reg, MEM_SMC, WSMC, OFF);
  155. REGSET(reg, MEM_SMC, BSMC, OFF);
  156. REGSET(reg, MEM_SMC, EW, OFF);
  157. REGSET(reg, MEM_SMC, PB, 1);
  158. REGSET(reg, MEM_SMC, PC, AL);
  159. REGSET(reg, MEM_SMC, PM, DIS);
  160. REGSET(reg, MEM_SMC, MW, 8);
  161. MEM_SMC(0) = reg;
  162. /* setup static CS0: timing */
  163. MEM_SMWED(0) = 0x2;
  164. MEM_SMOED(0) = 0x2;
  165. MEM_SMRD(0) = 0x6;
  166. MEM_SMWD(0) = 0x6;
  167. platform_add_devices(board_a9m9750dev_devices,
  168. ARRAY_SIZE(board_a9m9750dev_devices));
  169. }