lcd-panel.h 8.3 KB

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  1. /* lcd-panel.h
  2. $Id: lcd-panel.h,v 1.1.1.1 2007/06/12 07:27:14 eyryu Exp $
  3. written by Marc Singer
  4. 18 Jul 2005
  5. Copyright (C) 2005 Marc Singer
  6. -----------
  7. DESCRIPTION
  8. -----------
  9. Only one panel may be defined at a time.
  10. The pixel clock is calculated to be no greater than the target.
  11. Each timing value is accompanied by a specification comment.
  12. UNITS/MIN/TYP/MAX
  13. Most of the units will be in clocks.
  14. USE_RGB555
  15. Define this macro to configure the AMBA LCD controller to use an
  16. RGB555 encoding for the pels instead of the normal RGB565.
  17. LPD9520, LPD79524, LPD7A400, LPD7A404-10, LPD7A404-11
  18. These boards are best approximated by 555 for all panels. Some
  19. can use an extra low-order bit of blue in bit 16 of the color
  20. value, but we don't have a way to communicate this non-linear
  21. mapping to the kernel.
  22. */
  23. #if !defined (__LCD_PANEL_H__)
  24. # define __LCD_PANEL_H__
  25. #if defined (MACH_LPD79520)\
  26. || defined (MACH_LPD79524)\
  27. || defined (MACH_LPD7A400)\
  28. || defined (MACH_LPD7A404)
  29. # define USE_RGB555
  30. #endif
  31. struct clcd_panel_extra {
  32. unsigned int hrmode;
  33. unsigned int clsen;
  34. unsigned int spsen;
  35. unsigned int pcdel;
  36. unsigned int revdel;
  37. unsigned int lpdel;
  38. unsigned int spldel;
  39. unsigned int pc2del;
  40. };
  41. #define NS_TO_CLOCK(ns,c) ((((ns)*((c)/1000) + (1000000 - 1))/1000000))
  42. #define CLOCK_TO_DIV(e,c) (((c) + (e) - 1)/(e))
  43. #if defined CONFIG_FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
  44. /* Logic Product Development LCD 3.5" QVGA HRTFT -10 */
  45. /* Sharp PN LQ035Q7DB02 w/HRTFT controller chip */
  46. #define PIX_CLOCK_TARGET (6800000)
  47. #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
  48. #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
  49. static struct clcd_panel lcd_panel = {
  50. .mode = {
  51. .name = "3.5in QVGA (LQ035Q7DB02)",
  52. .xres = 240,
  53. .yres = 320,
  54. .pixclock = PIX_CLOCK,
  55. .left_margin = 16,
  56. .right_margin = 21,
  57. .upper_margin = 8, // line/8/8/8
  58. .lower_margin = 5,
  59. .hsync_len = 61,
  60. .vsync_len = NS_TO_CLOCK (60, PIX_CLOCK),
  61. .vmode = FB_VMODE_NONINTERLACED,
  62. },
  63. .width = -1,
  64. .height = -1,
  65. .tim2 = TIM2_IPC | (PIX_CLOCK_DIVIDER - 2),
  66. .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
  67. .bpp = 16,
  68. };
  69. #define HAS_LCD_PANEL_EXTRA
  70. static struct clcd_panel_extra lcd_panel_extra = {
  71. .hrmode = 1,
  72. .clsen = 1,
  73. .spsen = 1,
  74. .pcdel = 8,
  75. .revdel = 7,
  76. .lpdel = 13,
  77. .spldel = 77,
  78. .pc2del = 208,
  79. };
  80. #endif
  81. #if defined CONFIG_FB_ARMCLCD_SHARP_LQ057Q3DC02
  82. /* Logic Product Development LCD 5.7" QVGA -10 */
  83. /* Sharp PN LQ057Q3DC02 */
  84. /* QVGA mode, V/Q=LOW */
  85. /* From Sharp on 2006.1.3. I believe some of the values are incorrect
  86. * based on the datasheet.
  87. Timing0 TIMING1 TIMING2 CONTROL
  88. 0x140A0C4C 0x080504EF 0x013F380D 0x00000829
  89. HBP= 20 VBP= 8 BCD= 0
  90. HFP= 10 VFP= 5 CPL=319
  91. HSW= 12 VSW= 1 IOE= 0
  92. PPL= 19 LPP=239 IPC= 1
  93. IHS= 1
  94. IVS= 1
  95. ACB= 0
  96. CSEL= 0
  97. PCD= 13
  98. */
  99. /* The full horozontal cycle (Th) is clock/360/400/450. */
  100. /* The full vertical cycle (Tv) is line/251/262/280. */
  101. #define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */
  102. #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
  103. #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
  104. static struct clcd_panel lcd_panel = {
  105. .mode = {
  106. .name = "5.7in QVGA (LQ057Q3DC02)",
  107. .xres = 320,
  108. .yres = 240,
  109. .pixclock = PIX_CLOCK,
  110. .left_margin = 11,
  111. .right_margin = 400-11-320-2,
  112. .upper_margin = 7, // line/7/7/7
  113. .lower_margin = 262-7-240-2,
  114. .hsync_len = 2, // clk/2/96/200
  115. .vsync_len = 2, // line/2/-/34
  116. .vmode = FB_VMODE_NONINTERLACED,
  117. },
  118. .width = -1,
  119. .height = -1,
  120. .tim2 = TIM2_IHS | TIM2_IVS
  121. | (PIX_CLOCK_DIVIDER - 2),
  122. .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
  123. .bpp = 16,
  124. };
  125. #endif
  126. #if defined CONFIG_FB_ARMCLCD_SHARP_LQ64D343
  127. /* Logic Product Development LCD 6.4" VGA -10 */
  128. /* Sharp PN LQ64D343 */
  129. /* The full horozontal cycle (Th) is clock/750/800/900. */
  130. /* The full vertical cycle (Tv) is line/515/525/560. */
  131. #define PIX_CLOCK_TARGET (28330000)
  132. #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
  133. #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
  134. static struct clcd_panel lcd_panel = {
  135. .mode = {
  136. .name = "6.4in QVGA (LQ64D343)",
  137. .xres = 640,
  138. .yres = 480,
  139. .pixclock = PIX_CLOCK,
  140. .left_margin = 32,
  141. .right_margin = 800-32-640-96,
  142. .upper_margin = 32, // line/34/34/34
  143. .lower_margin = 540-32-480-2,
  144. .hsync_len = 96, // clk/2/96/200
  145. .vsync_len = 2, // line/2/-/34
  146. .vmode = FB_VMODE_NONINTERLACED,
  147. },
  148. .width = -1,
  149. .height = -1,
  150. .tim2 = TIM2_IHS | TIM2_IVS
  151. | (PIX_CLOCK_DIVIDER - 2),
  152. .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
  153. .bpp = 16,
  154. };
  155. #endif
  156. #if defined CONFIG_FB_ARMCLCD_SHARP_LQ10D368
  157. /* Logic Product Development LCD 10.4" VGA -10 */
  158. /* Sharp PN LQ10D368 */
  159. #define PIX_CLOCK_TARGET (28330000)
  160. #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
  161. #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
  162. static struct clcd_panel lcd_panel = {
  163. .mode = {
  164. .name = "10.4in VGA (LQ10D368)",
  165. .xres = 640,
  166. .yres = 480,
  167. .pixclock = PIX_CLOCK,
  168. .left_margin = 21,
  169. .right_margin = 15,
  170. .upper_margin = 34,
  171. .lower_margin = 5,
  172. .hsync_len = 96,
  173. .vsync_len = 16,
  174. .vmode = FB_VMODE_NONINTERLACED,
  175. },
  176. .width = -1,
  177. .height = -1,
  178. .tim2 = TIM2_IHS | TIM2_IVS
  179. | (PIX_CLOCK_DIVIDER - 2),
  180. .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
  181. .bpp = 16,
  182. };
  183. #endif
  184. #if defined CONFIG_FB_ARMCLCD_SHARP_LQ121S1DG41
  185. /* Logic Product Development LCD 12.1" SVGA -10 */
  186. /* Sharp PN LQ121S1DG41, was LQ121S1DG31 */
  187. /* Note that with a 99993900 Hz HCLK, it is not possible to hit the
  188. * target clock frequency range of 35MHz to 42MHz. */
  189. /* If the target pixel clock is substantially lower than the panel
  190. * spec, this is done to prevent the LCD display from glitching when
  191. * the CPU is under load. A pixel clock higher than 25MHz
  192. * (empirically determined) will compete with the CPU for bus cycles
  193. * for the Ethernet chip. However, even a pixel clock of 10MHz
  194. * competes with Compact Flash interface during some operations
  195. * (fdisk, e2fsck). And, at that speed the display may have a visible
  196. * flicker. */
  197. /* The full horozontal cycle (Th) is clock/832/1056/1395. */
  198. #define PIX_CLOCK_TARGET (20000000)
  199. #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
  200. #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
  201. static struct clcd_panel lcd_panel = {
  202. .mode = {
  203. .name = "12.1in SVGA (LQ121S1DG41)",
  204. .xres = 800,
  205. .yres = 600,
  206. .pixclock = PIX_CLOCK,
  207. .left_margin = 89, // ns/5/-/(1/PIX_CLOCK)-10
  208. .right_margin = 1056-800-89-128,
  209. .upper_margin = 23, // line/23/23/23
  210. .lower_margin = 44,
  211. .hsync_len = 128, // clk/2/128/200
  212. .vsync_len = 4, // line/2/4/6
  213. .vmode = FB_VMODE_NONINTERLACED,
  214. },
  215. .width = -1,
  216. .height = -1,
  217. .tim2 = TIM2_IHS | TIM2_IVS
  218. | (PIX_CLOCK_DIVIDER - 2),
  219. .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
  220. .bpp = 16,
  221. };
  222. #endif
  223. #if defined CONFIG_FB_ARMCLCD_HITACHI
  224. /* Hitachi*/
  225. /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
  226. #define PIX_CLOCK_TARGET (49000000)
  227. #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
  228. #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
  229. static struct clcd_panel lcd_panel = {
  230. .mode = {
  231. .name = "Hitachi 800x480",
  232. .xres = 800,
  233. .yres = 480,
  234. .pixclock = PIX_CLOCK,
  235. .left_margin = 88,
  236. .right_margin = 40,
  237. .upper_margin = 32,
  238. .lower_margin = 11,
  239. .hsync_len = 128,
  240. .vsync_len = 2,
  241. .vmode = FB_VMODE_NONINTERLACED,
  242. },
  243. .width = -1,
  244. .height = -1,
  245. .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS
  246. | (PIX_CLOCK_DIVIDER - 2),
  247. .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
  248. .bpp = 16,
  249. };
  250. #endif
  251. #if defined CONFIG_FB_ARMCLCD_AUO_A070VW01_WIDE
  252. /* AU Optotronics A070VW01 7.0 Wide Screen color Display*/
  253. /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
  254. #define PIX_CLOCK_TARGET (10000000)
  255. #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
  256. #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
  257. static struct clcd_panel lcd_panel = {
  258. .mode = {
  259. .name = "7.0in Wide (A070VW01)",
  260. .xres = 480,
  261. .yres = 234,
  262. .pixclock = PIX_CLOCK,
  263. .left_margin = 30,
  264. .right_margin = 25,
  265. .upper_margin = 14,
  266. .lower_margin = 12,
  267. .hsync_len = 100,
  268. .vsync_len = 1,
  269. .vmode = FB_VMODE_NONINTERLACED,
  270. },
  271. .width = -1,
  272. .height = -1,
  273. .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS
  274. | (PIX_CLOCK_DIVIDER - 2),
  275. .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
  276. .bpp = 16,
  277. };
  278. #endif
  279. #undef NS_TO_CLOCK
  280. #undef CLOCK_TO_DIV
  281. #endif /* __LCD_PANEL_H__ */