irq-lh7a404.c 4.2 KB

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  1. /* arch/arm/mach-lh7a40x/irq-lh7a404.c
  2. *
  3. * Copyright (C) 2004 Logic Product Development
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * version 2 as published by the Free Software Foundation.
  8. *
  9. */
  10. #include <linux/init.h>
  11. #include <linux/module.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/ptrace.h>
  14. #include <asm/hardware.h>
  15. #include <asm/irq.h>
  16. #include <asm/mach/irq.h>
  17. #include <asm/arch/irqs.h>
  18. #include "common.h"
  19. #define USE_PRIORITIES
  20. /* See Documentation/arm/Sharp-LH/VectoredInterruptController for more
  21. * information on using the vectored interrupt controller's
  22. * prioritizing feature. */
  23. static unsigned char irq_pri_vic1[] = {
  24. #if defined (USE_PRIORITIES)
  25. IRQ_GPIO3INTR, /* CPLD */
  26. IRQ_DMAM2P4, IRQ_DMAM2P5, /* AC97 */
  27. #endif
  28. };
  29. static unsigned char irq_pri_vic2[] = {
  30. #if defined (USE_PRIORITIES)
  31. IRQ_T3UI, /* Timer */
  32. IRQ_GPIO7INTR, /* CPLD */
  33. IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR,
  34. IRQ_LCDINTR, /* LCD */
  35. IRQ_TSCINTR, /* ADC/Touchscreen */
  36. #endif
  37. };
  38. /* CPU IRQ handling */
  39. static void lh7a404_vic1_mask_irq (u32 irq)
  40. {
  41. VIC1_INTENCLR = (1 << irq);
  42. }
  43. static void lh7a404_vic1_unmask_irq (u32 irq)
  44. {
  45. VIC1_INTEN = (1 << irq);
  46. }
  47. static void lh7a404_vic2_mask_irq (u32 irq)
  48. {
  49. VIC2_INTENCLR = (1 << (irq - 32));
  50. }
  51. static void lh7a404_vic2_unmask_irq (u32 irq)
  52. {
  53. VIC2_INTEN = (1 << (irq - 32));
  54. }
  55. static void lh7a404_vic1_ack_gpio_irq (u32 irq)
  56. {
  57. GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
  58. VIC1_INTENCLR = (1 << irq);
  59. }
  60. static void lh7a404_vic2_ack_gpio_irq (u32 irq)
  61. {
  62. GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
  63. VIC2_INTENCLR = (1 << irq);
  64. }
  65. static struct irq_chip lh7a404_vic1_chip = {
  66. .name = "VIC1",
  67. .ack = lh7a404_vic1_mask_irq, /* Because level-triggered */
  68. .mask = lh7a404_vic1_mask_irq,
  69. .unmask = lh7a404_vic1_unmask_irq,
  70. };
  71. static struct irq_chip lh7a404_vic2_chip = {
  72. .name = "VIC2",
  73. .ack = lh7a404_vic2_mask_irq, /* Because level-triggered */
  74. .mask = lh7a404_vic2_mask_irq,
  75. .unmask = lh7a404_vic2_unmask_irq,
  76. };
  77. static struct irq_chip lh7a404_gpio_vic1_chip = {
  78. .name = "GPIO-VIC1",
  79. .ack = lh7a404_vic1_ack_gpio_irq,
  80. .mask = lh7a404_vic1_mask_irq,
  81. .unmask = lh7a404_vic1_unmask_irq,
  82. };
  83. static struct irq_chip lh7a404_gpio_vic2_chip = {
  84. .name = "GPIO-VIC2",
  85. .ack = lh7a404_vic2_ack_gpio_irq,
  86. .mask = lh7a404_vic2_mask_irq,
  87. .unmask = lh7a404_vic2_unmask_irq,
  88. };
  89. /* IRQ initialization */
  90. #if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
  91. extern void* branch_irq_lh7a400;
  92. #endif
  93. void __init lh7a404_init_irq (void)
  94. {
  95. int irq;
  96. #if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
  97. #define NOP 0xe1a00000 /* mov r0, r0 */
  98. branch_irq_lh7a400 = NOP;
  99. #endif
  100. VIC1_INTENCLR = 0xffffffff;
  101. VIC2_INTENCLR = 0xffffffff;
  102. VIC1_INTSEL = 0; /* All IRQs */
  103. VIC2_INTSEL = 0; /* All IRQs */
  104. VIC1_NVADDR = VA_VIC1DEFAULT;
  105. VIC2_NVADDR = VA_VIC2DEFAULT;
  106. VIC1_VECTADDR = 0;
  107. VIC2_VECTADDR = 0;
  108. GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */
  109. barrier ();
  110. /* Install prioritized interrupts, if there are any. */
  111. /* The | 0x20*/
  112. for (irq = 0; irq < 16; ++irq) {
  113. (&VIC1_VAD0)[irq]
  114. = (irq < ARRAY_SIZE (irq_pri_vic1))
  115. ? (irq_pri_vic1[irq] | VA_VECTORED) : 0;
  116. (&VIC1_VECTCNTL0)[irq]
  117. = (irq < ARRAY_SIZE (irq_pri_vic1))
  118. ? (irq_pri_vic1[irq] | VIC_CNTL_ENABLE) : 0;
  119. (&VIC2_VAD0)[irq]
  120. = (irq < ARRAY_SIZE (irq_pri_vic2))
  121. ? (irq_pri_vic2[irq] | VA_VECTORED) : 0;
  122. (&VIC2_VECTCNTL0)[irq]
  123. = (irq < ARRAY_SIZE (irq_pri_vic2))
  124. ? (irq_pri_vic2[irq] | VIC_CNTL_ENABLE) : 0;
  125. }
  126. for (irq = 0; irq < NR_IRQS; ++irq) {
  127. switch (irq) {
  128. case IRQ_GPIO0INTR:
  129. case IRQ_GPIO1INTR:
  130. case IRQ_GPIO2INTR:
  131. case IRQ_GPIO3INTR:
  132. case IRQ_GPIO4INTR:
  133. case IRQ_GPIO5INTR:
  134. case IRQ_GPIO6INTR:
  135. case IRQ_GPIO7INTR:
  136. set_irq_chip (irq, irq < 32
  137. ? &lh7a404_gpio_vic1_chip
  138. : &lh7a404_gpio_vic2_chip);
  139. set_irq_handler (irq, handle_level_irq); /* OK default */
  140. break;
  141. default:
  142. set_irq_chip (irq, irq < 32
  143. ? &lh7a404_vic1_chip
  144. : &lh7a404_vic2_chip);
  145. set_irq_handler (irq, handle_level_irq);
  146. }
  147. set_irq_flags (irq, IRQF_VALID);
  148. }
  149. lh7a40x_init_board_irq ();
  150. }