arch-lpd7a40x.c 10.0 KB

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  1. /* arch/arm/mach-lh7a40x/arch-lpd7a40x.c
  2. *
  3. * Copyright (C) 2004 Logic Product Development
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * version 2 as published by the Free Software Foundation.
  8. *
  9. */
  10. #include <linux/tty.h>
  11. #include <linux/init.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/irq.h>
  15. #include <asm/hardware.h>
  16. #include <asm/setup.h>
  17. #include <asm/mach-types.h>
  18. #include <asm/mach/arch.h>
  19. #include <asm/irq.h>
  20. #include <asm/mach/irq.h>
  21. #include <asm/mach/map.h>
  22. #include "common.h"
  23. #define CPLD_INT_NETHERNET (1<<0)
  24. #define CPLD_INTMASK_ETHERNET (1<<2)
  25. #if defined (CONFIG_MACH_LPD7A400)
  26. # define CPLD_INT_NTOUCH (1<<1)
  27. # define CPLD_INTMASK_TOUCH (1<<3)
  28. # define CPLD_INT_PEN (1<<4)
  29. # define CPLD_INTMASK_PEN (1<<4)
  30. # define CPLD_INT_PIRQ (1<<4)
  31. #endif
  32. #define CPLD_INTMASK_CPLD (1<<7)
  33. #define CPLD_INT_CPLD (1<<6)
  34. #define CPLD_CONTROL_SWINT (1<<7) /* Disable all CPLD IRQs */
  35. #define CPLD_CONTROL_OCMSK (1<<6) /* Mask USB1 connect IRQ */
  36. #define CPLD_CONTROL_PDRV (1<<5) /* PCC_nDRV high */
  37. #define CPLD_CONTROL_USB1C (1<<4) /* USB1 connect IRQ active */
  38. #define CPLD_CONTROL_USB1P (1<<3) /* USB1 power disable */
  39. #define CPLD_CONTROL_AWKP (1<<2) /* Auto-wakeup disabled */
  40. #define CPLD_CONTROL_LCD_ENABLE (1<<1) /* LCD Vee enable */
  41. #define CPLD_CONTROL_WRLAN_NENABLE (1<<0) /* SMC91x power disable */
  42. static struct resource smc91x_resources[] = {
  43. [0] = {
  44. .start = CPLD00_PHYS,
  45. .end = CPLD00_PHYS + CPLD00_SIZE - 1, /* Only needs 16B */
  46. .flags = IORESOURCE_MEM,
  47. },
  48. [1] = {
  49. .start = IRQ_LPD7A40X_ETH_INT,
  50. .end = IRQ_LPD7A40X_ETH_INT,
  51. .flags = IORESOURCE_IRQ,
  52. },
  53. };
  54. static struct platform_device smc91x_device = {
  55. .name = "smc91x",
  56. .id = 0,
  57. .num_resources = ARRAY_SIZE(smc91x_resources),
  58. .resource = smc91x_resources,
  59. };
  60. static struct resource lh7a40x_usbclient_resources[] = {
  61. [0] = {
  62. .start = USB_PHYS,
  63. .end = (USB_PHYS + PAGE_SIZE),
  64. .flags = IORESOURCE_MEM,
  65. },
  66. [1] = {
  67. .start = IRQ_USB,
  68. .end = IRQ_USB,
  69. .flags = IORESOURCE_IRQ,
  70. },
  71. };
  72. static u64 lh7a40x_usbclient_dma_mask = 0xffffffffUL;
  73. static struct platform_device lh7a40x_usbclient_device = {
  74. // .name = "lh7a40x_udc",
  75. .name = "lh7-udc",
  76. .id = 0,
  77. .dev = {
  78. .dma_mask = &lh7a40x_usbclient_dma_mask,
  79. .coherent_dma_mask = 0xffffffffUL,
  80. },
  81. .num_resources = ARRAY_SIZE (lh7a40x_usbclient_resources),
  82. .resource = lh7a40x_usbclient_resources,
  83. };
  84. #if defined (CONFIG_ARCH_LH7A404)
  85. static struct resource lh7a404_usbhost_resources [] = {
  86. [0] = {
  87. .start = USBH_PHYS,
  88. .end = (USBH_PHYS + 0xFF),
  89. .flags = IORESOURCE_MEM,
  90. },
  91. [1] = {
  92. .start = IRQ_USHINTR,
  93. .end = IRQ_USHINTR,
  94. .flags = IORESOURCE_IRQ,
  95. },
  96. };
  97. static u64 lh7a404_usbhost_dma_mask = 0xffffffffUL;
  98. static struct platform_device lh7a404_usbhost_device = {
  99. .name = "lh7a404-ohci",
  100. .id = 0,
  101. .dev = {
  102. .dma_mask = &lh7a404_usbhost_dma_mask,
  103. .coherent_dma_mask = 0xffffffffUL,
  104. },
  105. .num_resources = ARRAY_SIZE (lh7a404_usbhost_resources),
  106. .resource = lh7a404_usbhost_resources,
  107. };
  108. #endif
  109. static struct platform_device* lpd7a40x_devs[] __initdata = {
  110. &smc91x_device,
  111. &lh7a40x_usbclient_device,
  112. #if defined (CONFIG_ARCH_LH7A404)
  113. &lh7a404_usbhost_device,
  114. #endif
  115. };
  116. extern void lpd7a400_map_io (void);
  117. static void __init lpd7a40x_init (void)
  118. {
  119. #if defined (CONFIG_MACH_LPD7A400)
  120. CPLD_CONTROL |= 0
  121. | CPLD_CONTROL_SWINT /* Disable software interrupt */
  122. | CPLD_CONTROL_OCMSK; /* Mask USB1 connection IRQ */
  123. CPLD_CONTROL &= ~(0
  124. | CPLD_CONTROL_LCD_ENABLE /* Disable LCD */
  125. | CPLD_CONTROL_WRLAN_NENABLE /* Enable SMC91x */
  126. );
  127. #endif
  128. #if defined (CONFIG_MACH_LPD7A404)
  129. CPLD_CONTROL &= ~(0
  130. | CPLD_CONTROL_WRLAN_NENABLE /* Enable SMC91x */
  131. );
  132. #endif
  133. platform_add_devices (lpd7a40x_devs, ARRAY_SIZE (lpd7a40x_devs));
  134. #if defined (CONFIG_FB_ARMCLCD)
  135. lh7a40x_clcd_init ();
  136. #endif
  137. }
  138. static void lh7a40x_ack_cpld_irq (u32 irq)
  139. {
  140. /* CPLD doesn't have ack capability, but some devices may */
  141. #if defined (CPLD_INTMASK_TOUCH)
  142. /* The touch control *must* mask the interrupt because the
  143. * interrupt bit is read by the driver to determine if the pen
  144. * is still down. */
  145. if (irq == IRQ_TOUCH)
  146. CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
  147. #endif
  148. }
  149. static void lh7a40x_mask_cpld_irq (u32 irq)
  150. {
  151. switch (irq) {
  152. case IRQ_LPD7A40X_ETH_INT:
  153. CPLD_INTERRUPTS |= CPLD_INTMASK_ETHERNET;
  154. break;
  155. #if defined (IRQ_TOUCH)
  156. case IRQ_TOUCH:
  157. CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
  158. break;
  159. #endif
  160. }
  161. }
  162. static void lh7a40x_unmask_cpld_irq (u32 irq)
  163. {
  164. switch (irq) {
  165. case IRQ_LPD7A40X_ETH_INT:
  166. CPLD_INTERRUPTS &= ~CPLD_INTMASK_ETHERNET;
  167. break;
  168. #if defined (IRQ_TOUCH)
  169. case IRQ_TOUCH:
  170. CPLD_INTERRUPTS &= ~CPLD_INTMASK_TOUCH;
  171. break;
  172. #endif
  173. }
  174. }
  175. static struct irq_chip lpd7a40x_cpld_chip = {
  176. .name = "CPLD",
  177. .ack = lh7a40x_ack_cpld_irq,
  178. .mask = lh7a40x_mask_cpld_irq,
  179. .unmask = lh7a40x_unmask_cpld_irq,
  180. };
  181. static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
  182. {
  183. unsigned int mask = CPLD_INTERRUPTS;
  184. desc->chip->ack (irq);
  185. if ((mask & (1<<0)) == 0) /* WLAN */
  186. IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT);
  187. #if defined (IRQ_TOUCH)
  188. if ((mask & (1<<1)) == 0) /* Touch */
  189. IRQ_DISPATCH (IRQ_TOUCH);
  190. #endif
  191. desc->chip->unmask (irq); /* Level-triggered need this */
  192. }
  193. void __init lh7a40x_init_board_irq (void)
  194. {
  195. int irq;
  196. /* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs.
  197. PF7 supports the CPLD.
  198. Rev B (v3.4): PF0, PF1, and PF2 are available IRQs.
  199. PF3 supports the CPLD.
  200. (Some) LPD7A404 prerelease boards report a version
  201. number of 0x16, but we force an override since the
  202. hardware is of the newer variety.
  203. */
  204. unsigned char cpld_version = CPLD_REVISION;
  205. int pinCPLD = (cpld_version == 0x28) ? 7 : 3;
  206. #if defined CONFIG_MACH_LPD7A404
  207. cpld_version = 0x34; /* Coerce LPD7A404 to RevB */
  208. #endif
  209. /* First, configure user controlled GPIOF interrupts */
  210. GPIO_PFDD &= ~0x0f; /* PF0-3 are inputs */
  211. GPIO_INTTYPE1 &= ~0x0f; /* PF0-3 are level triggered */
  212. GPIO_INTTYPE2 &= ~0x0f; /* PF0-3 are active low */
  213. barrier ();
  214. GPIO_GPIOFINTEN |= 0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */
  215. /* Then, configure CPLD interrupt */
  216. /* Disable all CPLD interrupts */
  217. #if defined (CONFIG_MACH_LPD7A400)
  218. CPLD_INTERRUPTS = CPLD_INTMASK_TOUCH | CPLD_INTMASK_PEN
  219. | CPLD_INTMASK_ETHERNET;
  220. /* *** FIXME: don't know why we need 7 and 4. 7 is way wrong
  221. and 4 is uncefined. */
  222. // (1<<7)|(1<<4)|(1<<3)|(1<<2);
  223. #endif
  224. #if defined (CONFIG_MACH_LPD7A404)
  225. CPLD_INTERRUPTS = CPLD_INTMASK_ETHERNET;
  226. /* *** FIXME: don't know why we need 6 and 5, neither is defined. */
  227. // (1<<6)|(1<<5)|(1<<3);
  228. #endif
  229. GPIO_PFDD &= ~(1 << pinCPLD); /* Make input */
  230. GPIO_INTTYPE1 &= ~(1 << pinCPLD); /* Level triggered */
  231. GPIO_INTTYPE2 &= ~(1 << pinCPLD); /* Active low */
  232. barrier ();
  233. GPIO_GPIOFINTEN |= (1 << pinCPLD); /* Enable */
  234. /* Cascade CPLD interrupts */
  235. for (irq = IRQ_BOARD_START;
  236. irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
  237. set_irq_chip (irq, &lpd7a40x_cpld_chip);
  238. set_irq_handler (irq, handle_level_irq);
  239. set_irq_flags (irq, IRQF_VALID);
  240. }
  241. set_irq_chained_handler ((cpld_version == 0x28)
  242. ? IRQ_CPLD_V28
  243. : IRQ_CPLD_V34,
  244. lpd7a40x_cpld_handler);
  245. }
  246. static struct map_desc lpd7a40x_io_desc[] __initdata = {
  247. {
  248. .virtual = IO_VIRT,
  249. .pfn = __phys_to_pfn(IO_PHYS),
  250. .length = IO_SIZE,
  251. .type = MT_DEVICE
  252. },
  253. { /* Mapping added to work around chip select problems */
  254. .virtual = IOBARRIER_VIRT,
  255. .pfn = __phys_to_pfn(IOBARRIER_PHYS),
  256. .length = IOBARRIER_SIZE,
  257. .type = MT_DEVICE
  258. },
  259. {
  260. .virtual = CF_VIRT,
  261. .pfn = __phys_to_pfn(CF_PHYS),
  262. .length = CF_SIZE,
  263. .type = MT_DEVICE
  264. },
  265. {
  266. .virtual = CPLD02_VIRT,
  267. .pfn = __phys_to_pfn(CPLD02_PHYS),
  268. .length = CPLD02_SIZE,
  269. .type = MT_DEVICE
  270. },
  271. {
  272. .virtual = CPLD06_VIRT,
  273. .pfn = __phys_to_pfn(CPLD06_PHYS),
  274. .length = CPLD06_SIZE,
  275. .type = MT_DEVICE
  276. },
  277. {
  278. .virtual = CPLD08_VIRT,
  279. .pfn = __phys_to_pfn(CPLD08_PHYS),
  280. .length = CPLD08_SIZE,
  281. .type = MT_DEVICE
  282. },
  283. {
  284. .virtual = CPLD08_VIRT,
  285. .pfn = __phys_to_pfn(CPLD08_PHYS),
  286. .length = CPLD08_SIZE,
  287. .type = MT_DEVICE
  288. },
  289. {
  290. .virtual = CPLD0A_VIRT,
  291. .pfn = __phys_to_pfn(CPLD0A_PHYS),
  292. .length = CPLD0A_SIZE,
  293. .type = MT_DEVICE
  294. },
  295. {
  296. .virtual = CPLD0C_VIRT,
  297. .pfn = __phys_to_pfn(CPLD0C_PHYS),
  298. .length = CPLD0C_SIZE,
  299. .type = MT_DEVICE
  300. },
  301. {
  302. .virtual = CPLD0E_VIRT,
  303. .pfn = __phys_to_pfn(CPLD0E_PHYS),
  304. .length = CPLD0E_SIZE,
  305. .type = MT_DEVICE
  306. },
  307. {
  308. .virtual = CPLD10_VIRT,
  309. .pfn = __phys_to_pfn(CPLD10_PHYS),
  310. .length = CPLD10_SIZE,
  311. .type = MT_DEVICE
  312. },
  313. {
  314. .virtual = CPLD12_VIRT,
  315. .pfn = __phys_to_pfn(CPLD12_PHYS),
  316. .length = CPLD12_SIZE,
  317. .type = MT_DEVICE
  318. },
  319. {
  320. .virtual = CPLD14_VIRT,
  321. .pfn = __phys_to_pfn(CPLD14_PHYS),
  322. .length = CPLD14_SIZE,
  323. .type = MT_DEVICE
  324. },
  325. {
  326. .virtual = CPLD16_VIRT,
  327. .pfn = __phys_to_pfn(CPLD16_PHYS),
  328. .length = CPLD16_SIZE,
  329. .type = MT_DEVICE
  330. },
  331. {
  332. .virtual = CPLD18_VIRT,
  333. .pfn = __phys_to_pfn(CPLD18_PHYS),
  334. .length = CPLD18_SIZE,
  335. .type = MT_DEVICE
  336. },
  337. {
  338. .virtual = CPLD1A_VIRT,
  339. .pfn = __phys_to_pfn(CPLD1A_PHYS),
  340. .length = CPLD1A_SIZE,
  341. .type = MT_DEVICE
  342. },
  343. };
  344. void __init
  345. lpd7a40x_map_io(void)
  346. {
  347. iotable_init (lpd7a40x_io_desc, ARRAY_SIZE (lpd7a40x_io_desc));
  348. }
  349. #ifdef CONFIG_MACH_LPD7A400
  350. MACHINE_START (LPD7A400, "Logic Product Development LPD7A400-10")
  351. /* Maintainer: Marc Singer */
  352. .phys_io = 0x80000000,
  353. .io_pg_offst = ((io_p2v (0x80000000))>>18) & 0xfffc,
  354. .boot_params = 0xc0000100,
  355. .map_io = lpd7a40x_map_io,
  356. .init_irq = lh7a400_init_irq,
  357. .timer = &lh7a40x_timer,
  358. .init_machine = lpd7a40x_init,
  359. MACHINE_END
  360. #endif
  361. #ifdef CONFIG_MACH_LPD7A404
  362. MACHINE_START (LPD7A404, "Logic Product Development LPD7A404-10")
  363. /* Maintainer: Marc Singer */
  364. .phys_io = 0x80000000,
  365. .io_pg_offst = ((io_p2v (0x80000000))>>18) & 0xfffc,
  366. .boot_params = 0xc0000100,
  367. .map_io = lpd7a40x_map_io,
  368. .init_irq = lh7a404_init_irq,
  369. .timer = &lh7a40x_timer,
  370. .init_machine = lpd7a40x_init,
  371. MACHINE_END
  372. #endif