pci.c 6.1 KB

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  1. /*
  2. * arch/arm/mach-ixp23xx/pci.c
  3. *
  4. * PCI routines for IXP23XX based systems
  5. *
  6. * Copyright (c) 2005 MontaVista Software, Inc.
  7. *
  8. * based on original code:
  9. *
  10. * Author: Naeem Afzal <naeem.m.afzal@intel.com>
  11. * Copyright 2002-2005 Intel Corp.
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. */
  18. #include <linux/sched.h>
  19. #include <linux/kernel.h>
  20. #include <linux/pci.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/mm.h>
  23. #include <linux/init.h>
  24. #include <linux/ioport.h>
  25. #include <linux/slab.h>
  26. #include <linux/delay.h>
  27. #include <asm/io.h>
  28. #include <asm/irq.h>
  29. #include <asm/sizes.h>
  30. #include <asm/system.h>
  31. #include <asm/mach/pci.h>
  32. #include <asm/mach-types.h>
  33. #include <asm/hardware.h>
  34. extern int (*external_fault) (unsigned long, struct pt_regs *);
  35. static volatile int pci_master_aborts = 0;
  36. #ifdef DEBUG
  37. #define DBG(x...) printk(x)
  38. #else
  39. #define DBG(x...)
  40. #endif
  41. int clear_master_aborts(void);
  42. static u32
  43. *ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
  44. {
  45. u32 *paddress;
  46. /*
  47. * Must be dword aligned
  48. */
  49. where &= ~3;
  50. /*
  51. * For top bus, generate type 0, else type 1
  52. */
  53. if (!bus_nr) {
  54. if (PCI_SLOT(devfn) >= 8)
  55. return 0;
  56. paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
  57. | (1 << (PCI_SLOT(devfn) + 16))
  58. | (PCI_FUNC(devfn) << 8) | where);
  59. } else {
  60. paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
  61. | (bus_nr << 16)
  62. | (PCI_SLOT(devfn) << 11)
  63. | (PCI_FUNC(devfn) << 8) | where);
  64. }
  65. return paddress;
  66. }
  67. /*
  68. * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
  69. * 0 and 3 are not valid indexes...
  70. */
  71. static u32 bytemask[] = {
  72. /*0*/ 0,
  73. /*1*/ 0xff,
  74. /*2*/ 0xffff,
  75. /*3*/ 0,
  76. /*4*/ 0xffffffff,
  77. };
  78. static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  79. int where, int size, u32 *value)
  80. {
  81. u32 n;
  82. u32 *addr;
  83. n = where % 4;
  84. DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
  85. bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
  86. addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
  87. if (!addr)
  88. return PCIBIOS_DEVICE_NOT_FOUND;
  89. pci_master_aborts = 0;
  90. *value = (*addr >> (8*n)) & bytemask[size];
  91. if (pci_master_aborts) {
  92. pci_master_aborts = 0;
  93. *value = 0xffffffff;
  94. return PCIBIOS_DEVICE_NOT_FOUND;
  95. }
  96. return PCIBIOS_SUCCESSFUL;
  97. }
  98. /*
  99. * We don't do error checking on the address for writes.
  100. * It's assumed that the user checked for the device existing first
  101. * by doing a read first.
  102. */
  103. static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
  104. int where, int size, u32 value)
  105. {
  106. u32 mask;
  107. u32 *addr;
  108. u32 temp;
  109. mask = ~(bytemask[size] << ((where % 0x4) * 8));
  110. addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
  111. if (!addr)
  112. return PCIBIOS_DEVICE_NOT_FOUND;
  113. temp = (u32) (value) << ((where % 0x4) * 8);
  114. *addr = (*addr & mask) | temp;
  115. clear_master_aborts();
  116. return PCIBIOS_SUCCESSFUL;
  117. }
  118. struct pci_ops ixp23xx_pci_ops = {
  119. .read = ixp23xx_pci_read_config,
  120. .write = ixp23xx_pci_write_config,
  121. };
  122. struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
  123. {
  124. return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata);
  125. }
  126. int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
  127. {
  128. volatile unsigned long temp;
  129. unsigned long flags;
  130. pci_master_aborts = 1;
  131. local_irq_save(flags);
  132. temp = *IXP23XX_PCI_CONTROL;
  133. /*
  134. * master abort and cmd tgt err
  135. */
  136. if (temp & ((1 << 8) | (1 << 5)))
  137. *IXP23XX_PCI_CONTROL = temp;
  138. temp = *IXP23XX_PCI_CMDSTAT;
  139. if (temp & (1 << 29))
  140. *IXP23XX_PCI_CMDSTAT = temp;
  141. local_irq_restore(flags);
  142. /*
  143. * If it was an imprecise abort, then we need to correct the
  144. * return address to be _after_ the instruction.
  145. */
  146. if (fsr & (1 << 10))
  147. regs->ARM_pc += 4;
  148. return 0;
  149. }
  150. int clear_master_aborts(void)
  151. {
  152. volatile u32 temp;
  153. temp = *IXP23XX_PCI_CONTROL;
  154. /*
  155. * master abort and cmd tgt err
  156. */
  157. if (temp & ((1 << 8) | (1 << 5)))
  158. *IXP23XX_PCI_CONTROL = temp;
  159. temp = *IXP23XX_PCI_CMDSTAT;
  160. if (temp & (1 << 29))
  161. *IXP23XX_PCI_CMDSTAT = temp;
  162. return 0;
  163. }
  164. static void __init ixp23xx_pci_common_init(void)
  165. {
  166. #ifdef __ARMEB__
  167. *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */
  168. #endif
  169. /*
  170. * ADDR_31 needs to be clear for PCI memory access to CPP memory
  171. */
  172. *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
  173. *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
  174. /*
  175. * Select correct memory for PCI inbound transactions
  176. */
  177. if (ixp23xx_cpp_boot()) {
  178. *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
  179. } else {
  180. *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
  181. /*
  182. * Enable coherency on A2 silicon.
  183. */
  184. if (arch_is_coherent())
  185. *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF;
  186. }
  187. }
  188. void __init ixp23xx_pci_preinit(void)
  189. {
  190. ixp23xx_pci_common_init();
  191. hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS,
  192. "PCI config cycle to non-existent device");
  193. *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
  194. }
  195. /*
  196. * Prevent PCI layer from seeing the inbound host-bridge resources
  197. */
  198. static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
  199. {
  200. int i;
  201. dev->class &= 0xff;
  202. dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
  203. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  204. dev->resource[i].start = 0;
  205. dev->resource[i].end = 0;
  206. dev->resource[i].flags = 0;
  207. }
  208. }
  209. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
  210. /*
  211. * IXP2300 systems often have large resource requirements, so we just
  212. * use our own resource space.
  213. */
  214. static struct resource ixp23xx_pci_mem_space = {
  215. .start = IXP23XX_PCI_MEM_START,
  216. .end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
  217. .flags = IORESOURCE_MEM,
  218. .name = "PCI Mem Space"
  219. };
  220. static struct resource ixp23xx_pci_io_space = {
  221. .start = 0x00000100,
  222. .end = 0x01ffffff,
  223. .flags = IORESOURCE_IO,
  224. .name = "PCI I/O Space"
  225. };
  226. int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
  227. {
  228. if (nr >= 1)
  229. return 0;
  230. sys->resource[0] = &ixp23xx_pci_io_space;
  231. sys->resource[1] = &ixp23xx_pci_mem_space;
  232. sys->resource[2] = NULL;
  233. return 1;
  234. }
  235. void ixp23xx_pci_slave_init(void)
  236. {
  237. ixp23xx_pci_common_init();
  238. }