ixdp2351.c 8.4 KB

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  1. /*
  2. * arch/arm/mach-ixp23xx/ixdp2351.c
  3. *
  4. * IXDP2351 board-specific routines
  5. *
  6. * Author: Deepak Saxena <dsaxena@plexity.net>
  7. *
  8. * Copyright 2005 (c) MontaVista Software, Inc.
  9. *
  10. * Based on 2.4 code Copyright 2004 (c) Intel Corporation
  11. *
  12. * This file is licensed under the terms of the GNU General Public
  13. * License version 2. This program is licensed "as is" without any
  14. * warranty of any kind, whether express or implied.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/sched.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/irq.h>
  22. #include <linux/serial.h>
  23. #include <linux/tty.h>
  24. #include <linux/bitops.h>
  25. #include <linux/ioport.h>
  26. #include <linux/serial.h>
  27. #include <linux/serial_8250.h>
  28. #include <linux/serial_core.h>
  29. #include <linux/device.h>
  30. #include <linux/mm.h>
  31. #include <linux/pci.h>
  32. #include <linux/mtd/physmap.h>
  33. #include <asm/types.h>
  34. #include <asm/setup.h>
  35. #include <asm/memory.h>
  36. #include <asm/hardware.h>
  37. #include <asm/mach-types.h>
  38. #include <asm/system.h>
  39. #include <asm/tlbflush.h>
  40. #include <asm/pgtable.h>
  41. #include <asm/mach/map.h>
  42. #include <asm/mach/irq.h>
  43. #include <asm/mach/arch.h>
  44. #include <asm/mach/irq.h>
  45. #include <asm/mach/pci.h>
  46. /*
  47. * IXDP2351 Interrupt Handling
  48. */
  49. static void ixdp2351_inta_mask(unsigned int irq)
  50. {
  51. *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(irq);
  52. }
  53. static void ixdp2351_inta_unmask(unsigned int irq)
  54. {
  55. *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
  56. }
  57. static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
  58. {
  59. u16 ex_interrupt =
  60. *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
  61. int i;
  62. desc->chip->mask(irq);
  63. for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
  64. if (ex_interrupt & (1 << i)) {
  65. struct irq_desc *cpld_desc;
  66. int cpld_irq =
  67. IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
  68. cpld_desc = irq_desc + cpld_irq;
  69. desc_handle_irq(cpld_irq, cpld_desc);
  70. }
  71. }
  72. desc->chip->unmask(irq);
  73. }
  74. static struct irq_chip ixdp2351_inta_chip = {
  75. .ack = ixdp2351_inta_mask,
  76. .mask = ixdp2351_inta_mask,
  77. .unmask = ixdp2351_inta_unmask
  78. };
  79. static void ixdp2351_intb_mask(unsigned int irq)
  80. {
  81. *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(irq);
  82. }
  83. static void ixdp2351_intb_unmask(unsigned int irq)
  84. {
  85. *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
  86. }
  87. static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
  88. {
  89. u16 ex_interrupt =
  90. *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
  91. int i;
  92. desc->chip->ack(irq);
  93. for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
  94. if (ex_interrupt & (1 << i)) {
  95. struct irq_desc *cpld_desc;
  96. int cpld_irq =
  97. IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
  98. cpld_desc = irq_desc + cpld_irq;
  99. desc_handle_irq(cpld_irq, cpld_desc);
  100. }
  101. }
  102. desc->chip->unmask(irq);
  103. }
  104. static struct irq_chip ixdp2351_intb_chip = {
  105. .ack = ixdp2351_intb_mask,
  106. .mask = ixdp2351_intb_mask,
  107. .unmask = ixdp2351_intb_unmask
  108. };
  109. void ixdp2351_init_irq(void)
  110. {
  111. int irq;
  112. /* Mask all interrupts from CPLD, disable simulation */
  113. *IXDP2351_CPLD_INTA_MASK_SET_REG = (u16) -1;
  114. *IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1;
  115. *IXDP2351_CPLD_INTA_SIM_REG = 0;
  116. *IXDP2351_CPLD_INTB_SIM_REG = 0;
  117. ixp23xx_init_irq();
  118. for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE);
  119. irq <
  120. IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM);
  121. irq++) {
  122. if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
  123. set_irq_flags(irq, IRQF_VALID);
  124. set_irq_handler(irq, handle_level_irq);
  125. set_irq_chip(irq, &ixdp2351_inta_chip);
  126. }
  127. }
  128. for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE);
  129. irq <
  130. IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM);
  131. irq++) {
  132. if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
  133. set_irq_flags(irq, IRQF_VALID);
  134. set_irq_handler(irq, handle_level_irq);
  135. set_irq_chip(irq, &ixdp2351_intb_chip);
  136. }
  137. }
  138. set_irq_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
  139. set_irq_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
  140. }
  141. /*
  142. * IXDP2351 PCI
  143. */
  144. /*
  145. * This board does not do normal PCI IRQ routing, or any
  146. * sort of swizzling, so we just need to check where on the
  147. * bus the device is and figure out what CPLD pin it is
  148. * being routed to.
  149. */
  150. #define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
  151. static int __init ixdp2351_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  152. {
  153. u8 bus = dev->bus->number;
  154. u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
  155. struct pci_bus *tmp_bus = dev->bus;
  156. /* Primary bus, no interrupts here */
  157. if (!bus)
  158. return -1;
  159. /* Lookup first leaf in bus tree */
  160. while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL))
  161. tmp_bus = tmp_bus->parent;
  162. /* Select between known bridges */
  163. switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
  164. /* Device is located after first bridge */
  165. case 0x0008:
  166. if (tmp_bus == dev->bus) {
  167. /* Device is located directy after first bridge */
  168. switch (devpin) {
  169. /* Onboard 82546 */
  170. case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
  171. return IRQ_IXDP2351_INTA_82546;
  172. case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
  173. return IRQ_IXDP2351_INTB_82546;
  174. /* PMC SLOT */
  175. case DEVPIN(0, 1): /* PMCP INTA# */
  176. case DEVPIN(2, 4): /* PMCS INTD# */
  177. return IRQ_IXDP2351_SPCI_PMC_INTA;
  178. case DEVPIN(0, 2): /* PMCP INTB# */
  179. case DEVPIN(2, 1): /* PMCS INTA# */
  180. return IRQ_IXDP2351_SPCI_PMC_INTB;
  181. case DEVPIN(0, 3): /* PMCP INTC# */
  182. case DEVPIN(2, 2): /* PMCS INTB# */
  183. return IRQ_IXDP2351_SPCI_PMC_INTC;
  184. case DEVPIN(0, 4): /* PMCP INTD# */
  185. case DEVPIN(2, 3): /* PMCS INTC# */
  186. return IRQ_IXDP2351_SPCI_PMC_INTD;
  187. }
  188. } else {
  189. /* Device is located indirectly after first bridge */
  190. /* Not supported now */
  191. return -1;
  192. }
  193. break;
  194. case 0x0010:
  195. if (tmp_bus == dev->bus) {
  196. /* Device is located directy after second bridge */
  197. /* Secondary bus of second bridge */
  198. switch (devpin) {
  199. case DEVPIN(0, 1): /* DB#0 */
  200. case DEVPIN(0, 2):
  201. case DEVPIN(0, 3):
  202. case DEVPIN(0, 4):
  203. return IRQ_IXDP2351_SPCI_DB_0;
  204. case DEVPIN(1, 1): /* DB#1 */
  205. case DEVPIN(1, 2):
  206. case DEVPIN(1, 3):
  207. case DEVPIN(1, 4):
  208. return IRQ_IXDP2351_SPCI_DB_1;
  209. case DEVPIN(2, 1): /* FIC1 */
  210. case DEVPIN(2, 2):
  211. case DEVPIN(2, 3):
  212. case DEVPIN(2, 4):
  213. case DEVPIN(3, 1): /* FIC2 */
  214. case DEVPIN(3, 2):
  215. case DEVPIN(3, 3):
  216. case DEVPIN(3, 4):
  217. return IRQ_IXDP2351_SPCI_FIC;
  218. }
  219. } else {
  220. /* Device is located indirectly after second bridge */
  221. /* Not supported now */
  222. return -1;
  223. }
  224. break;
  225. }
  226. return -1;
  227. }
  228. struct hw_pci ixdp2351_pci __initdata = {
  229. .nr_controllers = 1,
  230. .preinit = ixp23xx_pci_preinit,
  231. .setup = ixp23xx_pci_setup,
  232. .scan = ixp23xx_pci_scan_bus,
  233. .map_irq = ixdp2351_map_irq,
  234. };
  235. int __init ixdp2351_pci_init(void)
  236. {
  237. if (machine_is_ixdp2351())
  238. pci_common_init(&ixdp2351_pci);
  239. return 0;
  240. }
  241. subsys_initcall(ixdp2351_pci_init);
  242. /*
  243. * IXDP2351 Static Mapped I/O
  244. */
  245. static struct map_desc ixdp2351_io_desc[] __initdata = {
  246. {
  247. .virtual = IXDP2351_NP_VIRT_BASE,
  248. .pfn = __phys_to_pfn((u64)IXDP2351_NP_PHYS_BASE),
  249. .length = IXDP2351_NP_PHYS_SIZE,
  250. .type = MT_DEVICE
  251. }, {
  252. .virtual = IXDP2351_BB_BASE_VIRT,
  253. .pfn = __phys_to_pfn((u64)IXDP2351_BB_BASE_PHYS),
  254. .length = IXDP2351_BB_SIZE,
  255. .type = MT_DEVICE
  256. }
  257. };
  258. static void __init ixdp2351_map_io(void)
  259. {
  260. ixp23xx_map_io();
  261. iotable_init(ixdp2351_io_desc, ARRAY_SIZE(ixdp2351_io_desc));
  262. }
  263. static struct physmap_flash_data ixdp2351_flash_data = {
  264. .width = 1,
  265. };
  266. static struct resource ixdp2351_flash_resource = {
  267. .start = 0x90000000,
  268. .end = 0x93ffffff,
  269. .flags = IORESOURCE_MEM,
  270. };
  271. static struct platform_device ixdp2351_flash = {
  272. .name = "physmap-flash",
  273. .id = 0,
  274. .dev = {
  275. .platform_data = &ixdp2351_flash_data,
  276. },
  277. .num_resources = 1,
  278. .resource = &ixdp2351_flash_resource,
  279. };
  280. static void __init ixdp2351_init(void)
  281. {
  282. platform_device_register(&ixdp2351_flash);
  283. /*
  284. * Mark flash as writeable
  285. */
  286. IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
  287. IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
  288. IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
  289. IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
  290. ixp23xx_sys_init();
  291. }
  292. MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
  293. /* Maintainer: MontaVista Software, Inc. */
  294. .phys_io = IXP23XX_PERIPHERAL_PHYS,
  295. .io_pg_offst = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
  296. .map_io = ixdp2351_map_io,
  297. .init_irq = ixdp2351_init_irq,
  298. .timer = &ixp23xx_timer,
  299. .boot_params = 0x00000100,
  300. .init_machine = ixdp2351_init,
  301. MACHINE_END