core.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443
  1. /*
  2. * arch/arm/mach-ixp23xx/core.c
  3. *
  4. * Core routines for IXP23xx chips
  5. *
  6. * Author: Deepak Saxena <dsaxena@plexity.net>
  7. *
  8. * Copyright 2005 (c) MontaVista Software, Inc.
  9. *
  10. * Based on 2.4 code Copyright 2004 (c) Intel Corporation
  11. *
  12. * This file is licensed under the terms of the GNU General Public
  13. * License version 2. This program is licensed "as is" without any
  14. * warranty of any kind, whether express or implied.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/sched.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/serial.h>
  22. #include <linux/tty.h>
  23. #include <linux/bitops.h>
  24. #include <linux/serial.h>
  25. #include <linux/serial_8250.h>
  26. #include <linux/serial_core.h>
  27. #include <linux/device.h>
  28. #include <linux/mm.h>
  29. #include <linux/time.h>
  30. #include <linux/timex.h>
  31. #include <asm/types.h>
  32. #include <asm/setup.h>
  33. #include <asm/memory.h>
  34. #include <asm/hardware.h>
  35. #include <asm/mach-types.h>
  36. #include <asm/irq.h>
  37. #include <asm/system.h>
  38. #include <asm/tlbflush.h>
  39. #include <asm/pgtable.h>
  40. #include <asm/mach/map.h>
  41. #include <asm/mach/time.h>
  42. #include <asm/mach/irq.h>
  43. #include <asm/mach/arch.h>
  44. /*************************************************************************
  45. * Chip specific mappings shared by all IXP23xx systems
  46. *************************************************************************/
  47. static struct map_desc ixp23xx_io_desc[] __initdata = {
  48. { /* XSI-CPP CSRs */
  49. .virtual = IXP23XX_XSI2CPP_CSR_VIRT,
  50. .pfn = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS),
  51. .length = IXP23XX_XSI2CPP_CSR_SIZE,
  52. .type = MT_DEVICE,
  53. }, { /* Expansion Bus Config */
  54. .virtual = IXP23XX_EXP_CFG_VIRT,
  55. .pfn = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS),
  56. .length = IXP23XX_EXP_CFG_SIZE,
  57. .type = MT_DEVICE,
  58. }, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */
  59. .virtual = IXP23XX_PERIPHERAL_VIRT,
  60. .pfn = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS),
  61. .length = IXP23XX_PERIPHERAL_SIZE,
  62. .type = MT_DEVICE,
  63. }, { /* CAP CSRs */
  64. .virtual = IXP23XX_CAP_CSR_VIRT,
  65. .pfn = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS),
  66. .length = IXP23XX_CAP_CSR_SIZE,
  67. .type = MT_DEVICE,
  68. }, { /* MSF CSRs */
  69. .virtual = IXP23XX_MSF_CSR_VIRT,
  70. .pfn = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
  71. .length = IXP23XX_MSF_CSR_SIZE,
  72. .type = MT_DEVICE,
  73. }, { /* PCI I/O Space */
  74. .virtual = IXP23XX_PCI_IO_VIRT,
  75. .pfn = __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
  76. .length = IXP23XX_PCI_IO_SIZE,
  77. .type = MT_DEVICE,
  78. }, { /* PCI Config Space */
  79. .virtual = IXP23XX_PCI_CFG_VIRT,
  80. .pfn = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
  81. .length = IXP23XX_PCI_CFG_SIZE,
  82. .type = MT_DEVICE,
  83. }, { /* PCI local CFG CSRs */
  84. .virtual = IXP23XX_PCI_CREG_VIRT,
  85. .pfn = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS),
  86. .length = IXP23XX_PCI_CREG_SIZE,
  87. .type = MT_DEVICE,
  88. }, { /* PCI MEM Space */
  89. .virtual = IXP23XX_PCI_MEM_VIRT,
  90. .pfn = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS),
  91. .length = IXP23XX_PCI_MEM_SIZE,
  92. .type = MT_DEVICE,
  93. }
  94. };
  95. void __init ixp23xx_map_io(void)
  96. {
  97. iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
  98. }
  99. /***************************************************************************
  100. * IXP23xx Interrupt Handling
  101. ***************************************************************************/
  102. enum ixp23xx_irq_type {
  103. IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE
  104. };
  105. static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
  106. static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
  107. {
  108. int line = irq - IRQ_IXP23XX_GPIO6 + 6;
  109. u32 int_style;
  110. enum ixp23xx_irq_type irq_type;
  111. volatile u32 *int_reg;
  112. /*
  113. * Only GPIOs 6-15 are wired to interrupts on IXP23xx
  114. */
  115. if (line < 6 || line > 15)
  116. return -EINVAL;
  117. switch (type) {
  118. case IRQT_BOTHEDGE:
  119. int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
  120. irq_type = IXP23XX_IRQ_EDGE;
  121. break;
  122. case IRQT_RISING:
  123. int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
  124. irq_type = IXP23XX_IRQ_EDGE;
  125. break;
  126. case IRQT_FALLING:
  127. int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
  128. irq_type = IXP23XX_IRQ_EDGE;
  129. break;
  130. case IRQT_HIGH:
  131. int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
  132. irq_type = IXP23XX_IRQ_LEVEL;
  133. break;
  134. case IRQT_LOW:
  135. int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
  136. irq_type = IXP23XX_IRQ_LEVEL;
  137. break;
  138. default:
  139. return -EINVAL;
  140. }
  141. ixp23xx_config_irq(irq, irq_type);
  142. if (line >= 8) { /* pins 8-15 */
  143. line -= 8;
  144. int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R;
  145. } else { /* pins 0-7 */
  146. int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R;
  147. }
  148. /*
  149. * Clear pending interrupts
  150. */
  151. *IXP23XX_GPIO_GPISR = (1 << line);
  152. /* Clear the style for the appropriate pin */
  153. *int_reg &= ~(IXP23XX_GPIO_STYLE_MASK <<
  154. (line * IXP23XX_GPIO_STYLE_SIZE));
  155. /* Set the new style */
  156. *int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE));
  157. return 0;
  158. }
  159. static void ixp23xx_irq_mask(unsigned int irq)
  160. {
  161. volatile unsigned long *intr_reg;
  162. if (irq >= 56)
  163. irq += 8;
  164. intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
  165. *intr_reg &= ~(1 << (irq % 32));
  166. }
  167. static void ixp23xx_irq_ack(unsigned int irq)
  168. {
  169. int line = irq - IRQ_IXP23XX_GPIO6 + 6;
  170. if ((line < 6) || (line > 15))
  171. return;
  172. *IXP23XX_GPIO_GPISR = (1 << line);
  173. }
  174. /*
  175. * Level triggered interrupts on GPIO lines can only be cleared when the
  176. * interrupt condition disappears.
  177. */
  178. static void ixp23xx_irq_level_unmask(unsigned int irq)
  179. {
  180. volatile unsigned long *intr_reg;
  181. ixp23xx_irq_ack(irq);
  182. if (irq >= 56)
  183. irq += 8;
  184. intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
  185. *intr_reg |= (1 << (irq % 32));
  186. }
  187. static void ixp23xx_irq_edge_unmask(unsigned int irq)
  188. {
  189. volatile unsigned long *intr_reg;
  190. if (irq >= 56)
  191. irq += 8;
  192. intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
  193. *intr_reg |= (1 << (irq % 32));
  194. }
  195. static struct irq_chip ixp23xx_irq_level_chip = {
  196. .ack = ixp23xx_irq_mask,
  197. .mask = ixp23xx_irq_mask,
  198. .unmask = ixp23xx_irq_level_unmask,
  199. .set_type = ixp23xx_irq_set_type
  200. };
  201. static struct irq_chip ixp23xx_irq_edge_chip = {
  202. .ack = ixp23xx_irq_ack,
  203. .mask = ixp23xx_irq_mask,
  204. .unmask = ixp23xx_irq_edge_unmask,
  205. .set_type = ixp23xx_irq_set_type
  206. };
  207. static void ixp23xx_pci_irq_mask(unsigned int irq)
  208. {
  209. *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
  210. }
  211. static void ixp23xx_pci_irq_unmask(unsigned int irq)
  212. {
  213. *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
  214. }
  215. /*
  216. * TODO: Should this just be done at ASM level?
  217. */
  218. static void pci_handler(unsigned int irq, struct irq_desc *desc)
  219. {
  220. u32 pci_interrupt;
  221. unsigned int irqno;
  222. struct irq_desc *int_desc;
  223. pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
  224. desc->chip->ack(irq);
  225. /* See which PCI_INTA, or PCI_INTB interrupted */
  226. if (pci_interrupt & (1 << 26)) {
  227. irqno = IRQ_IXP23XX_INTB;
  228. } else if (pci_interrupt & (1 << 27)) {
  229. irqno = IRQ_IXP23XX_INTA;
  230. } else {
  231. BUG();
  232. }
  233. int_desc = irq_desc + irqno;
  234. desc_handle_irq(irqno, int_desc);
  235. desc->chip->unmask(irq);
  236. }
  237. static struct irq_chip ixp23xx_pci_irq_chip = {
  238. .ack = ixp23xx_pci_irq_mask,
  239. .mask = ixp23xx_pci_irq_mask,
  240. .unmask = ixp23xx_pci_irq_unmask
  241. };
  242. static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
  243. {
  244. switch (type) {
  245. case IXP23XX_IRQ_LEVEL:
  246. set_irq_chip(irq, &ixp23xx_irq_level_chip);
  247. set_irq_handler(irq, handle_level_irq);
  248. break;
  249. case IXP23XX_IRQ_EDGE:
  250. set_irq_chip(irq, &ixp23xx_irq_edge_chip);
  251. set_irq_handler(irq, handle_edge_irq);
  252. break;
  253. }
  254. set_irq_flags(irq, IRQF_VALID);
  255. }
  256. void __init ixp23xx_init_irq(void)
  257. {
  258. int irq;
  259. /* Route everything to IRQ */
  260. *IXP23XX_INTR_SEL1 = 0x0;
  261. *IXP23XX_INTR_SEL2 = 0x0;
  262. *IXP23XX_INTR_SEL3 = 0x0;
  263. *IXP23XX_INTR_SEL4 = 0x0;
  264. /* Mask all sources */
  265. *IXP23XX_INTR_EN1 = 0x0;
  266. *IXP23XX_INTR_EN2 = 0x0;
  267. *IXP23XX_INTR_EN3 = 0x0;
  268. *IXP23XX_INTR_EN4 = 0x0;
  269. /*
  270. * Configure all IRQs for level-sensitive operation
  271. */
  272. for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
  273. ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
  274. }
  275. for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
  276. set_irq_chip(irq, &ixp23xx_pci_irq_chip);
  277. set_irq_handler(irq, handle_level_irq);
  278. set_irq_flags(irq, IRQF_VALID);
  279. }
  280. set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
  281. }
  282. /*************************************************************************
  283. * Timer-tick functions for IXP23xx
  284. *************************************************************************/
  285. #define CLOCK_TICKS_PER_USEC (CLOCK_TICK_RATE / USEC_PER_SEC)
  286. static unsigned long next_jiffy_time;
  287. static unsigned long
  288. ixp23xx_gettimeoffset(void)
  289. {
  290. unsigned long elapsed;
  291. elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH);
  292. return elapsed / CLOCK_TICKS_PER_USEC;
  293. }
  294. static irqreturn_t
  295. ixp23xx_timer_interrupt(int irq, void *dev_id)
  296. {
  297. /* Clear Pending Interrupt by writing '1' to it */
  298. *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
  299. while ((signed long)(*IXP23XX_TIMER_CONT - next_jiffy_time) >= LATCH) {
  300. timer_tick();
  301. next_jiffy_time += LATCH;
  302. }
  303. return IRQ_HANDLED;
  304. }
  305. static struct irqaction ixp23xx_timer_irq = {
  306. .name = "IXP23xx Timer Tick",
  307. .handler = ixp23xx_timer_interrupt,
  308. .flags = IRQF_DISABLED | IRQF_TIMER,
  309. };
  310. void __init ixp23xx_init_timer(void)
  311. {
  312. /* Clear Pending Interrupt by writing '1' to it */
  313. *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
  314. /* Setup the Timer counter value */
  315. *IXP23XX_TIMER1_RELOAD =
  316. (LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE;
  317. *IXP23XX_TIMER_CONT = 0;
  318. next_jiffy_time = LATCH;
  319. /* Connect the interrupt handler and enable the interrupt */
  320. setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq);
  321. }
  322. struct sys_timer ixp23xx_timer = {
  323. .init = ixp23xx_init_timer,
  324. .offset = ixp23xx_gettimeoffset,
  325. };
  326. /*************************************************************************
  327. * IXP23xx Platform Initializaion
  328. *************************************************************************/
  329. static struct resource ixp23xx_uart_resources[] = {
  330. {
  331. .start = IXP23XX_UART1_PHYS,
  332. .end = IXP23XX_UART1_PHYS + 0x0fff,
  333. .flags = IORESOURCE_MEM
  334. }, {
  335. .start = IXP23XX_UART2_PHYS,
  336. .end = IXP23XX_UART2_PHYS + 0x0fff,
  337. .flags = IORESOURCE_MEM
  338. }
  339. };
  340. static struct plat_serial8250_port ixp23xx_uart_data[] = {
  341. {
  342. .mapbase = IXP23XX_UART1_PHYS,
  343. .membase = (char *)(IXP23XX_UART1_VIRT + 3),
  344. .irq = IRQ_IXP23XX_UART1,
  345. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  346. .iotype = UPIO_MEM,
  347. .regshift = 2,
  348. .uartclk = IXP23XX_UART_XTAL,
  349. }, {
  350. .mapbase = IXP23XX_UART2_PHYS,
  351. .membase = (char *)(IXP23XX_UART2_VIRT + 3),
  352. .irq = IRQ_IXP23XX_UART2,
  353. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  354. .iotype = UPIO_MEM,
  355. .regshift = 2,
  356. .uartclk = IXP23XX_UART_XTAL,
  357. },
  358. { },
  359. };
  360. static struct platform_device ixp23xx_uart = {
  361. .name = "serial8250",
  362. .id = 0,
  363. .dev.platform_data = ixp23xx_uart_data,
  364. .num_resources = 2,
  365. .resource = ixp23xx_uart_resources,
  366. };
  367. static struct platform_device *ixp23xx_devices[] __initdata = {
  368. &ixp23xx_uart,
  369. };
  370. void __init ixp23xx_sys_init(void)
  371. {
  372. *IXP23XX_EXP_UNIT_FUSE |= 0xf;
  373. platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
  374. }