ixdp2x01.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460
  1. /*
  2. * arch/arm/mach-ixp2000/ixdp2x01.c
  3. *
  4. * Code common to Intel IXDP2401 and IXDP2801 platforms
  5. *
  6. * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
  7. * Maintainer: Deepak Saxena <dsaxena@plexity.net>
  8. *
  9. * Copyright (C) 2002-2003 Intel Corp.
  10. * Copyright (C) 2003-2004 MontaVista Software, Inc.
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License as published by the
  14. * Free Software Foundation; either version 2 of the License, or (at your
  15. * option) any later version.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/mm.h>
  20. #include <linux/sched.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/bitops.h>
  23. #include <linux/pci.h>
  24. #include <linux/ioport.h>
  25. #include <linux/slab.h>
  26. #include <linux/delay.h>
  27. #include <linux/serial.h>
  28. #include <linux/tty.h>
  29. #include <linux/serial_core.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/serial_8250.h>
  32. #include <asm/io.h>
  33. #include <asm/irq.h>
  34. #include <asm/pgtable.h>
  35. #include <asm/page.h>
  36. #include <asm/system.h>
  37. #include <asm/hardware.h>
  38. #include <asm/mach-types.h>
  39. #include <asm/mach/pci.h>
  40. #include <asm/mach/map.h>
  41. #include <asm/mach/irq.h>
  42. #include <asm/mach/time.h>
  43. #include <asm/mach/arch.h>
  44. #include <asm/mach/flash.h>
  45. /*************************************************************************
  46. * IXDP2x01 IRQ Handling
  47. *************************************************************************/
  48. static void ixdp2x01_irq_mask(unsigned int irq)
  49. {
  50. ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
  51. IXP2000_BOARD_IRQ_MASK(irq));
  52. }
  53. static void ixdp2x01_irq_unmask(unsigned int irq)
  54. {
  55. ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
  56. IXP2000_BOARD_IRQ_MASK(irq));
  57. }
  58. static u32 valid_irq_mask;
  59. static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
  60. {
  61. u32 ex_interrupt;
  62. int i;
  63. desc->chip->mask(irq);
  64. ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
  65. if (!ex_interrupt) {
  66. printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n");
  67. return;
  68. }
  69. for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
  70. if (ex_interrupt & (1 << i)) {
  71. struct irq_desc *cpld_desc;
  72. int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
  73. cpld_desc = irq_desc + cpld_irq;
  74. desc_handle_irq(cpld_irq, cpld_desc);
  75. }
  76. }
  77. desc->chip->unmask(irq);
  78. }
  79. static struct irq_chip ixdp2x01_irq_chip = {
  80. .mask = ixdp2x01_irq_mask,
  81. .ack = ixdp2x01_irq_mask,
  82. .unmask = ixdp2x01_irq_unmask
  83. };
  84. /*
  85. * We only do anything if we are the master NPU on the board.
  86. * The slave NPU only has the ethernet chip going directly to
  87. * the PCIB interrupt input.
  88. */
  89. void __init ixdp2x01_init_irq(void)
  90. {
  91. int irq = 0;
  92. /* initialize chip specific interrupts */
  93. ixp2000_init_irq();
  94. if (machine_is_ixdp2401())
  95. valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
  96. else
  97. valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
  98. /* Mask all interrupts from CPLD, disable simulation */
  99. ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
  100. ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0);
  101. for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
  102. if (irq & valid_irq_mask) {
  103. set_irq_chip(irq, &ixdp2x01_irq_chip);
  104. set_irq_handler(irq, handle_level_irq);
  105. set_irq_flags(irq, IRQF_VALID);
  106. } else {
  107. set_irq_flags(irq, 0);
  108. }
  109. }
  110. /* Hook into PCI interrupts */
  111. set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
  112. }
  113. /*************************************************************************
  114. * IXDP2x01 memory map
  115. *************************************************************************/
  116. static struct map_desc ixdp2x01_io_desc __initdata = {
  117. .virtual = IXDP2X01_VIRT_CPLD_BASE,
  118. .pfn = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE),
  119. .length = IXDP2X01_CPLD_REGION_SIZE,
  120. .type = MT_DEVICE
  121. };
  122. static void __init ixdp2x01_map_io(void)
  123. {
  124. ixp2000_map_io();
  125. iotable_init(&ixdp2x01_io_desc, 1);
  126. }
  127. /*************************************************************************
  128. * IXDP2x01 serial ports
  129. *************************************************************************/
  130. static struct plat_serial8250_port ixdp2x01_serial_port1[] = {
  131. {
  132. .mapbase = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
  133. .membase = (char *)IXDP2X01_UART1_VIRT_BASE,
  134. .irq = IRQ_IXDP2X01_UART1,
  135. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  136. .iotype = UPIO_MEM32,
  137. .regshift = 2,
  138. .uartclk = IXDP2X01_UART_CLK,
  139. },
  140. { }
  141. };
  142. static struct resource ixdp2x01_uart_resource1 = {
  143. .start = IXDP2X01_UART1_PHYS_BASE,
  144. .end = IXDP2X01_UART1_PHYS_BASE + 0xffff,
  145. .flags = IORESOURCE_MEM,
  146. };
  147. static struct platform_device ixdp2x01_serial_device1 = {
  148. .name = "serial8250",
  149. .id = PLAT8250_DEV_PLATFORM1,
  150. .dev = {
  151. .platform_data = ixdp2x01_serial_port1,
  152. },
  153. .num_resources = 1,
  154. .resource = &ixdp2x01_uart_resource1,
  155. };
  156. static struct plat_serial8250_port ixdp2x01_serial_port2[] = {
  157. {
  158. .mapbase = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
  159. .membase = (char *)IXDP2X01_UART2_VIRT_BASE,
  160. .irq = IRQ_IXDP2X01_UART2,
  161. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  162. .iotype = UPIO_MEM32,
  163. .regshift = 2,
  164. .uartclk = IXDP2X01_UART_CLK,
  165. },
  166. { }
  167. };
  168. static struct resource ixdp2x01_uart_resource2 = {
  169. .start = IXDP2X01_UART2_PHYS_BASE,
  170. .end = IXDP2X01_UART2_PHYS_BASE + 0xffff,
  171. .flags = IORESOURCE_MEM,
  172. };
  173. static struct platform_device ixdp2x01_serial_device2 = {
  174. .name = "serial8250",
  175. .id = PLAT8250_DEV_PLATFORM2,
  176. .dev = {
  177. .platform_data = ixdp2x01_serial_port2,
  178. },
  179. .num_resources = 1,
  180. .resource = &ixdp2x01_uart_resource2,
  181. };
  182. static void ixdp2x01_uart_init(void)
  183. {
  184. platform_device_register(&ixdp2x01_serial_device1);
  185. platform_device_register(&ixdp2x01_serial_device2);
  186. }
  187. /*************************************************************************
  188. * IXDP2x01 timer tick configuration
  189. *************************************************************************/
  190. static unsigned int ixdp2x01_clock;
  191. static int __init ixdp2x01_clock_setup(char *str)
  192. {
  193. ixdp2x01_clock = simple_strtoul(str, NULL, 10);
  194. return 1;
  195. }
  196. __setup("ixdp2x01_clock=", ixdp2x01_clock_setup);
  197. static void __init ixdp2x01_timer_init(void)
  198. {
  199. if (!ixdp2x01_clock)
  200. ixdp2x01_clock = 50000000;
  201. ixp2000_init_time(ixdp2x01_clock);
  202. }
  203. static struct sys_timer ixdp2x01_timer = {
  204. .init = ixdp2x01_timer_init,
  205. .offset = ixp2000_gettimeoffset,
  206. };
  207. /*************************************************************************
  208. * IXDP2x01 PCI
  209. *************************************************************************/
  210. void __init ixdp2x01_pci_preinit(void)
  211. {
  212. ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
  213. ixp2000_pci_preinit();
  214. pcibios_setup("firmware");
  215. }
  216. #define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
  217. static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  218. {
  219. u8 bus = dev->bus->number;
  220. u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
  221. struct pci_bus *tmp_bus = dev->bus;
  222. /* Primary bus, no interrupts here */
  223. if (bus == 0) {
  224. return -1;
  225. }
  226. /* Lookup first leaf in bus tree */
  227. while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
  228. tmp_bus = tmp_bus->parent;
  229. }
  230. /* Select between known bridges */
  231. switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
  232. /* Device is located after first MB bridge */
  233. case 0x0008:
  234. if (tmp_bus == dev->bus) {
  235. /* Device is located directy after first MB bridge */
  236. switch (devpin) {
  237. case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
  238. if (machine_is_ixdp2401())
  239. return IRQ_IXDP2401_INTA_82546;
  240. return -1;
  241. case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
  242. if (machine_is_ixdp2401())
  243. return IRQ_IXDP2401_INTB_82546;
  244. return -1;
  245. case DEVPIN(0, 1): /* PMC INTA# */
  246. return IRQ_IXDP2X01_SPCI_PMC_INTA;
  247. case DEVPIN(0, 2): /* PMC INTB# */
  248. return IRQ_IXDP2X01_SPCI_PMC_INTB;
  249. case DEVPIN(0, 3): /* PMC INTC# */
  250. return IRQ_IXDP2X01_SPCI_PMC_INTC;
  251. case DEVPIN(0, 4): /* PMC INTD# */
  252. return IRQ_IXDP2X01_SPCI_PMC_INTD;
  253. }
  254. }
  255. break;
  256. case 0x0010:
  257. if (tmp_bus == dev->bus) {
  258. /* Device is located directy after second MB bridge */
  259. /* Secondary bus of second bridge */
  260. switch (devpin) {
  261. case DEVPIN(0, 1): /* DB#0 */
  262. return IRQ_IXDP2X01_SPCI_DB_0;
  263. case DEVPIN(1, 1): /* DB#1 */
  264. return IRQ_IXDP2X01_SPCI_DB_1;
  265. }
  266. } else {
  267. /* Device is located indirectly after second MB bridge */
  268. /* Not supported now */
  269. }
  270. break;
  271. }
  272. return -1;
  273. }
  274. static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
  275. {
  276. sys->mem_offset = 0xe0000000;
  277. if (machine_is_ixdp2801() || machine_is_ixdp28x5())
  278. sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16);
  279. return ixp2000_pci_setup(nr, sys);
  280. }
  281. struct hw_pci ixdp2x01_pci __initdata = {
  282. .nr_controllers = 1,
  283. .setup = ixdp2x01_pci_setup,
  284. .preinit = ixdp2x01_pci_preinit,
  285. .scan = ixp2000_pci_scan_bus,
  286. .map_irq = ixdp2x01_pci_map_irq,
  287. };
  288. int __init ixdp2x01_pci_init(void)
  289. {
  290. if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\
  291. machine_is_ixdp28x5())
  292. pci_common_init(&ixdp2x01_pci);
  293. return 0;
  294. }
  295. subsys_initcall(ixdp2x01_pci_init);
  296. /*************************************************************************
  297. * IXDP2x01 Machine Intialization
  298. *************************************************************************/
  299. static struct flash_platform_data ixdp2x01_flash_platform_data = {
  300. .map_name = "cfi_probe",
  301. .width = 1,
  302. };
  303. static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
  304. {
  305. ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
  306. ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
  307. return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
  308. }
  309. static struct ixp2000_flash_data ixdp2x01_flash_data = {
  310. .platform_data = &ixdp2x01_flash_platform_data,
  311. .bank_setup = ixdp2x01_flash_bank_setup
  312. };
  313. static struct resource ixdp2x01_flash_resource = {
  314. .start = 0xc4000000,
  315. .end = 0xc4000000 + 0x01ffffff,
  316. .flags = IORESOURCE_MEM,
  317. };
  318. static struct platform_device ixdp2x01_flash = {
  319. .name = "IXP2000-Flash",
  320. .id = 0,
  321. .dev = {
  322. .platform_data = &ixdp2x01_flash_data,
  323. },
  324. .num_resources = 1,
  325. .resource = &ixdp2x01_flash_resource,
  326. };
  327. static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = {
  328. .sda_pin = IXDP2X01_GPIO_SDA,
  329. .scl_pin = IXDP2X01_GPIO_SCL,
  330. };
  331. static struct platform_device ixdp2x01_i2c_controller = {
  332. .name = "IXP2000-I2C",
  333. .id = 0,
  334. .dev = {
  335. .platform_data = &ixdp2x01_i2c_gpio_pins,
  336. },
  337. .num_resources = 0
  338. };
  339. static struct platform_device *ixdp2x01_devices[] __initdata = {
  340. &ixdp2x01_flash,
  341. &ixdp2x01_i2c_controller
  342. };
  343. static void __init ixdp2x01_init_machine(void)
  344. {
  345. ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
  346. (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
  347. ixdp2x01_flash_data.nr_banks =
  348. ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);
  349. platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
  350. ixp2000_uart_init();
  351. ixdp2x01_uart_init();
  352. }
  353. #ifdef CONFIG_ARCH_IXDP2401
  354. MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
  355. /* Maintainer: MontaVista Software, Inc. */
  356. .phys_io = IXP2000_UART_PHYS_BASE,
  357. .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
  358. .boot_params = 0x00000100,
  359. .map_io = ixdp2x01_map_io,
  360. .init_irq = ixdp2x01_init_irq,
  361. .timer = &ixdp2x01_timer,
  362. .init_machine = ixdp2x01_init_machine,
  363. MACHINE_END
  364. #endif
  365. #ifdef CONFIG_ARCH_IXDP2801
  366. MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
  367. /* Maintainer: MontaVista Software, Inc. */
  368. .phys_io = IXP2000_UART_PHYS_BASE,
  369. .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
  370. .boot_params = 0x00000100,
  371. .map_io = ixdp2x01_map_io,
  372. .init_irq = ixdp2x01_init_irq,
  373. .timer = &ixdp2x01_timer,
  374. .init_machine = ixdp2x01_init_machine,
  375. MACHINE_END
  376. /*
  377. * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel
  378. * changed the machine ID in the bootloader
  379. */
  380. MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
  381. /* Maintainer: MontaVista Software, Inc. */
  382. .phys_io = IXP2000_UART_PHYS_BASE,
  383. .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
  384. .boot_params = 0x00000100,
  385. .map_io = ixdp2x01_map_io,
  386. .init_irq = ixdp2x01_init_irq,
  387. .timer = &ixdp2x01_timer,
  388. .init_machine = ixdp2x01_init_machine,
  389. MACHINE_END
  390. #endif