core.c 15 KB

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  1. /*
  2. * arch/arm/mach-ixp2000/core.c
  3. *
  4. * Common routines used by all IXP2400/2800 based platforms.
  5. *
  6. * Author: Deepak Saxena <dsaxena@plexity.net>
  7. *
  8. * Copyright 2004 (C) MontaVista Software, Inc.
  9. *
  10. * Based on work Copyright (C) 2002-2003 Intel Corporation
  11. *
  12. * This file is licensed under the terms of the GNU General Public
  13. * License version 2. This program is licensed "as is" without any
  14. * warranty of any kind, whether express or implied.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/sched.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/irq.h>
  22. #include <linux/serial.h>
  23. #include <linux/tty.h>
  24. #include <linux/bitops.h>
  25. #include <linux/serial_8250.h>
  26. #include <linux/mm.h>
  27. #include <asm/types.h>
  28. #include <asm/setup.h>
  29. #include <asm/memory.h>
  30. #include <asm/hardware.h>
  31. #include <asm/irq.h>
  32. #include <asm/system.h>
  33. #include <asm/tlbflush.h>
  34. #include <asm/pgtable.h>
  35. #include <asm/mach/map.h>
  36. #include <asm/mach/time.h>
  37. #include <asm/mach/irq.h>
  38. #include <asm/arch/gpio.h>
  39. static DEFINE_SPINLOCK(ixp2000_slowport_lock);
  40. static unsigned long ixp2000_slowport_irq_flags;
  41. /*************************************************************************
  42. * Slowport access routines
  43. *************************************************************************/
  44. void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
  45. {
  46. spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
  47. old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
  48. old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
  49. old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
  50. old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
  51. old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
  52. ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
  53. ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
  54. ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
  55. ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
  56. ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
  57. }
  58. void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
  59. {
  60. ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
  61. ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
  62. ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
  63. ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
  64. ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
  65. spin_unlock_irqrestore(&ixp2000_slowport_lock,
  66. ixp2000_slowport_irq_flags);
  67. }
  68. /*************************************************************************
  69. * Chip specific mappings shared by all IXP2000 systems
  70. *************************************************************************/
  71. static struct map_desc ixp2000_io_desc[] __initdata = {
  72. {
  73. .virtual = IXP2000_CAP_VIRT_BASE,
  74. .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
  75. .length = IXP2000_CAP_SIZE,
  76. .type = MT_IXP2000_DEVICE,
  77. }, {
  78. .virtual = IXP2000_INTCTL_VIRT_BASE,
  79. .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
  80. .length = IXP2000_INTCTL_SIZE,
  81. .type = MT_IXP2000_DEVICE,
  82. }, {
  83. .virtual = IXP2000_PCI_CREG_VIRT_BASE,
  84. .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
  85. .length = IXP2000_PCI_CREG_SIZE,
  86. .type = MT_IXP2000_DEVICE,
  87. }, {
  88. .virtual = IXP2000_PCI_CSR_VIRT_BASE,
  89. .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
  90. .length = IXP2000_PCI_CSR_SIZE,
  91. .type = MT_IXP2000_DEVICE,
  92. }, {
  93. .virtual = IXP2000_MSF_VIRT_BASE,
  94. .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
  95. .length = IXP2000_MSF_SIZE,
  96. .type = MT_IXP2000_DEVICE,
  97. }, {
  98. .virtual = IXP2000_SCRATCH_RING_VIRT_BASE,
  99. .pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
  100. .length = IXP2000_SCRATCH_RING_SIZE,
  101. .type = MT_IXP2000_DEVICE,
  102. }, {
  103. .virtual = IXP2000_SRAM0_VIRT_BASE,
  104. .pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
  105. .length = IXP2000_SRAM0_SIZE,
  106. .type = MT_IXP2000_DEVICE,
  107. }, {
  108. .virtual = IXP2000_PCI_IO_VIRT_BASE,
  109. .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
  110. .length = IXP2000_PCI_IO_SIZE,
  111. .type = MT_IXP2000_DEVICE,
  112. }, {
  113. .virtual = IXP2000_PCI_CFG0_VIRT_BASE,
  114. .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
  115. .length = IXP2000_PCI_CFG0_SIZE,
  116. .type = MT_IXP2000_DEVICE,
  117. }, {
  118. .virtual = IXP2000_PCI_CFG1_VIRT_BASE,
  119. .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
  120. .length = IXP2000_PCI_CFG1_SIZE,
  121. .type = MT_IXP2000_DEVICE,
  122. }
  123. };
  124. void __init ixp2000_map_io(void)
  125. {
  126. /*
  127. * On IXP2400 CPUs we need to use MT_IXP2000_DEVICE so that
  128. * XCB=101 (to avoid triggering erratum #66), and given that
  129. * this mode speeds up I/O accesses and we have write buffer
  130. * flushes in the right places anyway, it doesn't hurt to use
  131. * XCB=101 for all IXP2000s.
  132. */
  133. iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
  134. /* Set slowport to 8-bit mode. */
  135. ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
  136. }
  137. /*************************************************************************
  138. * Serial port support for IXP2000
  139. *************************************************************************/
  140. static struct plat_serial8250_port ixp2000_serial_port[] = {
  141. {
  142. .mapbase = IXP2000_UART_PHYS_BASE,
  143. .membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
  144. .irq = IRQ_IXP2000_UART,
  145. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  146. .iotype = UPIO_MEM,
  147. .regshift = 2,
  148. .uartclk = 50000000,
  149. },
  150. { },
  151. };
  152. static struct resource ixp2000_uart_resource = {
  153. .start = IXP2000_UART_PHYS_BASE,
  154. .end = IXP2000_UART_PHYS_BASE + 0x1f,
  155. .flags = IORESOURCE_MEM,
  156. };
  157. static struct platform_device ixp2000_serial_device = {
  158. .name = "serial8250",
  159. .id = PLAT8250_DEV_PLATFORM,
  160. .dev = {
  161. .platform_data = ixp2000_serial_port,
  162. },
  163. .num_resources = 1,
  164. .resource = &ixp2000_uart_resource,
  165. };
  166. void __init ixp2000_uart_init(void)
  167. {
  168. platform_device_register(&ixp2000_serial_device);
  169. }
  170. /*************************************************************************
  171. * Timer-tick functions for IXP2000
  172. *************************************************************************/
  173. static unsigned ticks_per_jiffy;
  174. static unsigned ticks_per_usec;
  175. static unsigned next_jiffy_time;
  176. static volatile unsigned long *missing_jiffy_timer_csr;
  177. unsigned long ixp2000_gettimeoffset (void)
  178. {
  179. unsigned long offset;
  180. offset = next_jiffy_time - *missing_jiffy_timer_csr;
  181. return offset / ticks_per_usec;
  182. }
  183. static int ixp2000_timer_interrupt(int irq, void *dev_id)
  184. {
  185. write_seqlock(&xtime_lock);
  186. /* clear timer 1 */
  187. ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
  188. while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
  189. >= ticks_per_jiffy) {
  190. timer_tick();
  191. next_jiffy_time -= ticks_per_jiffy;
  192. }
  193. write_sequnlock(&xtime_lock);
  194. return IRQ_HANDLED;
  195. }
  196. static struct irqaction ixp2000_timer_irq = {
  197. .name = "IXP2000 Timer Tick",
  198. .flags = IRQF_DISABLED | IRQF_TIMER,
  199. .handler = ixp2000_timer_interrupt,
  200. };
  201. void __init ixp2000_init_time(unsigned long tick_rate)
  202. {
  203. ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
  204. ticks_per_usec = tick_rate / 1000000;
  205. /*
  206. * We use timer 1 as our timer interrupt.
  207. */
  208. ixp2000_reg_write(IXP2000_T1_CLR, 0);
  209. ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
  210. ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
  211. /*
  212. * We use a second timer as a monotonic counter for tracking
  213. * missed jiffies. The IXP2000 has four timers, but if we're
  214. * on an A-step IXP2800, timer 2 and 3 don't work, so on those
  215. * chips we use timer 4. Timer 4 is the only timer that can
  216. * be used for the watchdog, so we use timer 2 if we're on a
  217. * non-buggy chip.
  218. */
  219. if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
  220. printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
  221. ixp2000_reg_write(IXP2000_T4_CLR, 0);
  222. ixp2000_reg_write(IXP2000_T4_CLD, -1);
  223. ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
  224. missing_jiffy_timer_csr = IXP2000_T4_CSR;
  225. } else {
  226. ixp2000_reg_write(IXP2000_T2_CLR, 0);
  227. ixp2000_reg_write(IXP2000_T2_CLD, -1);
  228. ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
  229. missing_jiffy_timer_csr = IXP2000_T2_CSR;
  230. }
  231. next_jiffy_time = 0xffffffff;
  232. /* register for interrupt */
  233. setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
  234. }
  235. /*************************************************************************
  236. * GPIO helpers
  237. *************************************************************************/
  238. static unsigned long GPIO_IRQ_falling_edge;
  239. static unsigned long GPIO_IRQ_rising_edge;
  240. static unsigned long GPIO_IRQ_level_low;
  241. static unsigned long GPIO_IRQ_level_high;
  242. static void update_gpio_int_csrs(void)
  243. {
  244. ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
  245. ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
  246. ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
  247. ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
  248. }
  249. void gpio_line_config(int line, int direction)
  250. {
  251. unsigned long flags;
  252. local_irq_save(flags);
  253. if (direction == GPIO_OUT) {
  254. /* if it's an output, it ain't an interrupt anymore */
  255. GPIO_IRQ_falling_edge &= ~(1 << line);
  256. GPIO_IRQ_rising_edge &= ~(1 << line);
  257. GPIO_IRQ_level_low &= ~(1 << line);
  258. GPIO_IRQ_level_high &= ~(1 << line);
  259. update_gpio_int_csrs();
  260. ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
  261. } else if (direction == GPIO_IN) {
  262. ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
  263. }
  264. local_irq_restore(flags);
  265. }
  266. EXPORT_SYMBOL(gpio_line_config);
  267. /*************************************************************************
  268. * IRQ handling IXP2000
  269. *************************************************************************/
  270. static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
  271. {
  272. int i;
  273. unsigned long status = *IXP2000_GPIO_INST;
  274. for (i = 0; i <= 7; i++) {
  275. if (status & (1<<i)) {
  276. desc = irq_desc + i + IRQ_IXP2000_GPIO0;
  277. desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc);
  278. }
  279. }
  280. }
  281. static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
  282. {
  283. int line = irq - IRQ_IXP2000_GPIO0;
  284. /*
  285. * First, configure this GPIO line as an input.
  286. */
  287. ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
  288. /*
  289. * Then, set the proper trigger type.
  290. */
  291. if (type & IRQT_FALLING)
  292. GPIO_IRQ_falling_edge |= 1 << line;
  293. else
  294. GPIO_IRQ_falling_edge &= ~(1 << line);
  295. if (type & IRQT_RISING)
  296. GPIO_IRQ_rising_edge |= 1 << line;
  297. else
  298. GPIO_IRQ_rising_edge &= ~(1 << line);
  299. if (type & IRQT_LOW)
  300. GPIO_IRQ_level_low |= 1 << line;
  301. else
  302. GPIO_IRQ_level_low &= ~(1 << line);
  303. if (type & IRQT_HIGH)
  304. GPIO_IRQ_level_high |= 1 << line;
  305. else
  306. GPIO_IRQ_level_high &= ~(1 << line);
  307. update_gpio_int_csrs();
  308. return 0;
  309. }
  310. static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
  311. {
  312. ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
  313. ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
  314. ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
  315. ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
  316. }
  317. static void ixp2000_GPIO_irq_mask(unsigned int irq)
  318. {
  319. ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
  320. }
  321. static void ixp2000_GPIO_irq_unmask(unsigned int irq)
  322. {
  323. ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
  324. }
  325. static struct irq_chip ixp2000_GPIO_irq_chip = {
  326. .ack = ixp2000_GPIO_irq_mask_ack,
  327. .mask = ixp2000_GPIO_irq_mask,
  328. .unmask = ixp2000_GPIO_irq_unmask,
  329. .set_type = ixp2000_GPIO_irq_type,
  330. };
  331. static void ixp2000_pci_irq_mask(unsigned int irq)
  332. {
  333. unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
  334. if (irq == IRQ_IXP2000_PCIA)
  335. ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
  336. else if (irq == IRQ_IXP2000_PCIB)
  337. ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
  338. }
  339. static void ixp2000_pci_irq_unmask(unsigned int irq)
  340. {
  341. unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
  342. if (irq == IRQ_IXP2000_PCIA)
  343. ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
  344. else if (irq == IRQ_IXP2000_PCIB)
  345. ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
  346. }
  347. /*
  348. * Error interrupts. These are used extensively by the microengine drivers
  349. */
  350. static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
  351. {
  352. int i;
  353. unsigned long status = *IXP2000_IRQ_ERR_STATUS;
  354. for(i = 31; i >= 0; i--) {
  355. if(status & (1 << i)) {
  356. desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
  357. desc_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc);
  358. }
  359. }
  360. }
  361. static void ixp2000_err_irq_mask(unsigned int irq)
  362. {
  363. ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
  364. (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
  365. }
  366. static void ixp2000_err_irq_unmask(unsigned int irq)
  367. {
  368. ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
  369. (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
  370. }
  371. static struct irq_chip ixp2000_err_irq_chip = {
  372. .ack = ixp2000_err_irq_mask,
  373. .mask = ixp2000_err_irq_mask,
  374. .unmask = ixp2000_err_irq_unmask
  375. };
  376. static struct irq_chip ixp2000_pci_irq_chip = {
  377. .ack = ixp2000_pci_irq_mask,
  378. .mask = ixp2000_pci_irq_mask,
  379. .unmask = ixp2000_pci_irq_unmask
  380. };
  381. static void ixp2000_irq_mask(unsigned int irq)
  382. {
  383. ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
  384. }
  385. static void ixp2000_irq_unmask(unsigned int irq)
  386. {
  387. ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
  388. }
  389. static struct irq_chip ixp2000_irq_chip = {
  390. .ack = ixp2000_irq_mask,
  391. .mask = ixp2000_irq_mask,
  392. .unmask = ixp2000_irq_unmask
  393. };
  394. void __init ixp2000_init_irq(void)
  395. {
  396. int irq;
  397. /*
  398. * Mask all sources
  399. */
  400. ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
  401. ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
  402. /* clear all GPIO edge/level detects */
  403. ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
  404. ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
  405. ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
  406. ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
  407. ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
  408. /* clear PCI interrupt sources */
  409. ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
  410. /*
  411. * Certain bits in the IRQ status register of the
  412. * IXP2000 are reserved. Instead of trying to map
  413. * things non 1:1 from bit position to IRQ number,
  414. * we mark the reserved IRQs as invalid. This makes
  415. * our mask/unmask code much simpler.
  416. */
  417. for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
  418. if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
  419. set_irq_chip(irq, &ixp2000_irq_chip);
  420. set_irq_handler(irq, handle_level_irq);
  421. set_irq_flags(irq, IRQF_VALID);
  422. } else set_irq_flags(irq, 0);
  423. }
  424. for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
  425. if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
  426. IXP2000_VALID_ERR_IRQ_MASK) {
  427. set_irq_chip(irq, &ixp2000_err_irq_chip);
  428. set_irq_handler(irq, handle_level_irq);
  429. set_irq_flags(irq, IRQF_VALID);
  430. }
  431. else
  432. set_irq_flags(irq, 0);
  433. }
  434. set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
  435. for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
  436. set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
  437. set_irq_handler(irq, handle_level_irq);
  438. set_irq_flags(irq, IRQF_VALID);
  439. }
  440. set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
  441. /*
  442. * Enable PCI irqs. The actual PCI[AB] decoding is done in
  443. * entry-macro.S, so we don't need a chained handler for the
  444. * PCI interrupt source.
  445. */
  446. ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
  447. for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
  448. set_irq_chip(irq, &ixp2000_pci_irq_chip);
  449. set_irq_handler(irq, handle_level_irq);
  450. set_irq_flags(irq, IRQF_VALID);
  451. }
  452. }