setup.c 9.7 KB

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  1. /*
  2. * iop13xx platform Initialization
  3. * Copyright (c) 2005-2006, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  16. * Place - Suite 330, Boston, MA 02111-1307 USA.
  17. *
  18. */
  19. #include <linux/serial_8250.h>
  20. #ifdef CONFIG_MTD_PHYSMAP
  21. #include <linux/mtd/physmap.h>
  22. #endif
  23. #include <asm/mach/map.h>
  24. #include <asm/hardware.h>
  25. #include <asm/irq.h>
  26. #include <asm/io.h>
  27. #define IOP13XX_UART_XTAL 33334000
  28. #define IOP13XX_SETUP_DEBUG 0
  29. #define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
  30. /* Standard IO mapping for all IOP13XX based systems
  31. */
  32. static struct map_desc iop13xx_std_desc[] __initdata = {
  33. { /* mem mapped registers */
  34. .virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
  35. .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
  36. .length = IOP13XX_PMMR_SIZE,
  37. .type = MT_DEVICE,
  38. }, { /* PCIE IO space */
  39. .virtual = IOP13XX_PCIE_LOWER_IO_VA,
  40. .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
  41. .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
  42. .type = MT_DEVICE,
  43. }, { /* PCIX IO space */
  44. .virtual = IOP13XX_PCIX_LOWER_IO_VA,
  45. .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
  46. .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
  47. .type = MT_DEVICE,
  48. },
  49. };
  50. static struct resource iop13xx_uart0_resources[] = {
  51. [0] = {
  52. .start = IOP13XX_UART0_PHYS,
  53. .end = IOP13XX_UART0_PHYS + 0x3f,
  54. .flags = IORESOURCE_MEM,
  55. },
  56. [1] = {
  57. .start = IRQ_IOP13XX_UART0,
  58. .end = IRQ_IOP13XX_UART0,
  59. .flags = IORESOURCE_IRQ
  60. }
  61. };
  62. static struct resource iop13xx_uart1_resources[] = {
  63. [0] = {
  64. .start = IOP13XX_UART1_PHYS,
  65. .end = IOP13XX_UART1_PHYS + 0x3f,
  66. .flags = IORESOURCE_MEM,
  67. },
  68. [1] = {
  69. .start = IRQ_IOP13XX_UART1,
  70. .end = IRQ_IOP13XX_UART1,
  71. .flags = IORESOURCE_IRQ
  72. }
  73. };
  74. static struct plat_serial8250_port iop13xx_uart0_data[] = {
  75. {
  76. .membase = (char*)(IOP13XX_UART0_VIRT),
  77. .mapbase = (IOP13XX_UART0_PHYS),
  78. .irq = IRQ_IOP13XX_UART0,
  79. .uartclk = IOP13XX_UART_XTAL,
  80. .regshift = 2,
  81. .iotype = UPIO_MEM,
  82. .flags = UPF_SKIP_TEST,
  83. },
  84. { },
  85. };
  86. static struct plat_serial8250_port iop13xx_uart1_data[] = {
  87. {
  88. .membase = (char*)(IOP13XX_UART1_VIRT),
  89. .mapbase = (IOP13XX_UART1_PHYS),
  90. .irq = IRQ_IOP13XX_UART1,
  91. .uartclk = IOP13XX_UART_XTAL,
  92. .regshift = 2,
  93. .iotype = UPIO_MEM,
  94. .flags = UPF_SKIP_TEST,
  95. },
  96. { },
  97. };
  98. /* The ids are fixed up later in iop13xx_platform_init */
  99. static struct platform_device iop13xx_uart0 = {
  100. .name = "serial8250",
  101. .id = 0,
  102. .dev.platform_data = iop13xx_uart0_data,
  103. .num_resources = 2,
  104. .resource = iop13xx_uart0_resources,
  105. };
  106. static struct platform_device iop13xx_uart1 = {
  107. .name = "serial8250",
  108. .id = 0,
  109. .dev.platform_data = iop13xx_uart1_data,
  110. .num_resources = 2,
  111. .resource = iop13xx_uart1_resources
  112. };
  113. static struct resource iop13xx_i2c_0_resources[] = {
  114. [0] = {
  115. .start = IOP13XX_I2C0_PHYS,
  116. .end = IOP13XX_I2C0_PHYS + 0x18,
  117. .flags = IORESOURCE_MEM,
  118. },
  119. [1] = {
  120. .start = IRQ_IOP13XX_I2C_0,
  121. .end = IRQ_IOP13XX_I2C_0,
  122. .flags = IORESOURCE_IRQ
  123. }
  124. };
  125. static struct resource iop13xx_i2c_1_resources[] = {
  126. [0] = {
  127. .start = IOP13XX_I2C1_PHYS,
  128. .end = IOP13XX_I2C1_PHYS + 0x18,
  129. .flags = IORESOURCE_MEM,
  130. },
  131. [1] = {
  132. .start = IRQ_IOP13XX_I2C_1,
  133. .end = IRQ_IOP13XX_I2C_1,
  134. .flags = IORESOURCE_IRQ
  135. }
  136. };
  137. static struct resource iop13xx_i2c_2_resources[] = {
  138. [0] = {
  139. .start = IOP13XX_I2C2_PHYS,
  140. .end = IOP13XX_I2C2_PHYS + 0x18,
  141. .flags = IORESOURCE_MEM,
  142. },
  143. [1] = {
  144. .start = IRQ_IOP13XX_I2C_2,
  145. .end = IRQ_IOP13XX_I2C_2,
  146. .flags = IORESOURCE_IRQ
  147. }
  148. };
  149. /* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
  150. * we just use the same device name.
  151. */
  152. /* The ids are fixed up later in iop13xx_platform_init */
  153. static struct platform_device iop13xx_i2c_0_controller = {
  154. .name = "IOP3xx-I2C",
  155. .id = 0,
  156. .num_resources = 2,
  157. .resource = iop13xx_i2c_0_resources
  158. };
  159. static struct platform_device iop13xx_i2c_1_controller = {
  160. .name = "IOP3xx-I2C",
  161. .id = 0,
  162. .num_resources = 2,
  163. .resource = iop13xx_i2c_1_resources
  164. };
  165. static struct platform_device iop13xx_i2c_2_controller = {
  166. .name = "IOP3xx-I2C",
  167. .id = 0,
  168. .num_resources = 2,
  169. .resource = iop13xx_i2c_2_resources
  170. };
  171. #ifdef CONFIG_MTD_PHYSMAP
  172. /* PBI Flash Device
  173. */
  174. static struct physmap_flash_data iq8134x_flash_data = {
  175. .width = 2,
  176. };
  177. static struct resource iq8134x_flash_resource = {
  178. .start = IQ81340_FLASHBASE,
  179. .end = 0,
  180. .flags = IORESOURCE_MEM,
  181. };
  182. static struct platform_device iq8134x_flash = {
  183. .name = "physmap-flash",
  184. .id = 0,
  185. .dev = { .platform_data = &iq8134x_flash_data, },
  186. .num_resources = 1,
  187. .resource = &iq8134x_flash_resource,
  188. };
  189. static unsigned long iq8134x_probe_flash_size(void)
  190. {
  191. uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
  192. int i;
  193. char query[3];
  194. unsigned long size = 0;
  195. int width = iq8134x_flash_data.width;
  196. if (flash_addr) {
  197. /* send CFI 'query' command */
  198. writew(0x98, flash_addr);
  199. /* check for CFI compliance */
  200. for (i = 0; i < 3 * width; i += width)
  201. query[i / width] = readb(flash_addr + (0x10 * width) + i);
  202. /* read the size */
  203. if (memcmp(query, "QRY", 3) == 0)
  204. size = 1 << readb(flash_addr + (0x27 * width));
  205. /* send CFI 'read array' command */
  206. writew(0xff, flash_addr);
  207. iounmap(flash_addr);
  208. }
  209. return size;
  210. }
  211. #endif
  212. void __init iop13xx_map_io(void)
  213. {
  214. /* Initialize the Static Page Table maps */
  215. iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
  216. }
  217. static int init_uart = 0;
  218. static int init_i2c = 0;
  219. void __init iop13xx_platform_init(void)
  220. {
  221. int i;
  222. u32 uart_idx, i2c_idx, plat_idx;
  223. struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
  224. /* set the bases so we can read the device id */
  225. iop13xx_set_atu_mmr_bases();
  226. memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
  227. if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
  228. switch (iop13xx_dev_id()) {
  229. /* enable both uarts on iop341 and iop342 */
  230. case 0x3380:
  231. case 0x3384:
  232. case 0x3388:
  233. case 0x338c:
  234. case 0x3382:
  235. case 0x3386:
  236. case 0x338a:
  237. case 0x338e:
  238. init_uart |= IOP13XX_INIT_UART_0;
  239. init_uart |= IOP13XX_INIT_UART_1;
  240. break;
  241. /* only enable uart 1 */
  242. default:
  243. init_uart |= IOP13XX_INIT_UART_1;
  244. }
  245. }
  246. if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
  247. switch (iop13xx_dev_id()) {
  248. /* enable all i2c units on iop341 and iop342 */
  249. case 0x3380:
  250. case 0x3384:
  251. case 0x3388:
  252. case 0x338c:
  253. case 0x3382:
  254. case 0x3386:
  255. case 0x338a:
  256. case 0x338e:
  257. init_i2c |= IOP13XX_INIT_I2C_0;
  258. init_i2c |= IOP13XX_INIT_I2C_1;
  259. init_i2c |= IOP13XX_INIT_I2C_2;
  260. break;
  261. /* only enable i2c 1 and 2 */
  262. default:
  263. init_i2c |= IOP13XX_INIT_I2C_1;
  264. init_i2c |= IOP13XX_INIT_I2C_2;
  265. }
  266. }
  267. plat_idx = 0;
  268. uart_idx = 0;
  269. i2c_idx = 0;
  270. /* uart 1 (if enabled) is ttyS0 */
  271. if (init_uart & IOP13XX_INIT_UART_1) {
  272. PRINTK("Adding uart1 to platform device list\n");
  273. iop13xx_uart1.id = uart_idx++;
  274. iop13xx_devices[plat_idx++] = &iop13xx_uart1;
  275. }
  276. if (init_uart & IOP13XX_INIT_UART_0) {
  277. PRINTK("Adding uart0 to platform device list\n");
  278. iop13xx_uart0.id = uart_idx++;
  279. iop13xx_devices[plat_idx++] = &iop13xx_uart0;
  280. }
  281. for(i = 0; i < IQ81340_NUM_I2C; i++) {
  282. if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
  283. printk("Adding i2c%d to platform device list\n", i);
  284. switch(init_i2c & (1 << i)) {
  285. case IOP13XX_INIT_I2C_0:
  286. iop13xx_i2c_0_controller.id = i2c_idx++;
  287. iop13xx_devices[plat_idx++] =
  288. &iop13xx_i2c_0_controller;
  289. break;
  290. case IOP13XX_INIT_I2C_1:
  291. iop13xx_i2c_1_controller.id = i2c_idx++;
  292. iop13xx_devices[plat_idx++] =
  293. &iop13xx_i2c_1_controller;
  294. break;
  295. case IOP13XX_INIT_I2C_2:
  296. iop13xx_i2c_2_controller.id = i2c_idx++;
  297. iop13xx_devices[plat_idx++] =
  298. &iop13xx_i2c_2_controller;
  299. break;
  300. }
  301. }
  302. #ifdef CONFIG_MTD_PHYSMAP
  303. iq8134x_flash_resource.end = iq8134x_flash_resource.start +
  304. iq8134x_probe_flash_size() - 1;
  305. if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
  306. iop13xx_devices[plat_idx++] = &iq8134x_flash;
  307. else
  308. printk(KERN_ERR "%s: Failed to probe flash size\n", __FUNCTION__);
  309. #endif
  310. platform_add_devices(iop13xx_devices, plat_idx);
  311. }
  312. static int __init iop13xx_init_uart_setup(char *str)
  313. {
  314. if (str) {
  315. while (*str != '\0') {
  316. switch(*str) {
  317. case '0':
  318. init_uart |= IOP13XX_INIT_UART_0;
  319. break;
  320. case '1':
  321. init_uart |= IOP13XX_INIT_UART_1;
  322. break;
  323. case ',':
  324. case '=':
  325. break;
  326. default:
  327. PRINTK("\"iop13xx_init_uart\" malformed"
  328. " at character: \'%c\'", *str);
  329. *(str + 1) = '\0';
  330. init_uart = IOP13XX_INIT_UART_DEFAULT;
  331. }
  332. str++;
  333. }
  334. }
  335. return 1;
  336. }
  337. static int __init iop13xx_init_i2c_setup(char *str)
  338. {
  339. if (str) {
  340. while (*str != '\0') {
  341. switch(*str) {
  342. case '0':
  343. init_i2c |= IOP13XX_INIT_I2C_0;
  344. break;
  345. case '1':
  346. init_i2c |= IOP13XX_INIT_I2C_1;
  347. break;
  348. case '2':
  349. init_i2c |= IOP13XX_INIT_I2C_2;
  350. break;
  351. case ',':
  352. case '=':
  353. break;
  354. default:
  355. PRINTK("\"iop13xx_init_i2c\" malformed"
  356. " at character: \'%c\'", *str);
  357. *(str + 1) = '\0';
  358. init_i2c = IOP13XX_INIT_I2C_DEFAULT;
  359. }
  360. str++;
  361. }
  362. }
  363. return 1;
  364. }
  365. __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
  366. __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);