pci.c 31 KB

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  1. /*
  2. * iop13xx PCI support
  3. * Copyright (c) 2005-2006, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  16. * Place - Suite 330, Boston, MA 02111-1307 USA.
  17. *
  18. */
  19. #include <linux/pci.h>
  20. #include <linux/delay.h>
  21. #include <asm/irq.h>
  22. #include <asm/hardware.h>
  23. #include <asm/sizes.h>
  24. #include <asm/mach/pci.h>
  25. #include <asm/arch/pci.h>
  26. #define IOP13XX_PCI_DEBUG 0
  27. #define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
  28. u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
  29. u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
  30. static struct pci_bus *pci_bus_atux = 0;
  31. static struct pci_bus *pci_bus_atue = 0;
  32. u32 iop13xx_atue_mem_base;
  33. u32 iop13xx_atux_mem_base;
  34. size_t iop13xx_atue_mem_size;
  35. size_t iop13xx_atux_mem_size;
  36. unsigned long iop13xx_pcibios_min_io = 0;
  37. unsigned long iop13xx_pcibios_min_mem = 0;
  38. EXPORT_SYMBOL(iop13xx_atue_mem_base);
  39. EXPORT_SYMBOL(iop13xx_atux_mem_base);
  40. EXPORT_SYMBOL(iop13xx_atue_mem_size);
  41. EXPORT_SYMBOL(iop13xx_atux_mem_size);
  42. int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */
  43. static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first
  44. access */
  45. /* Scan the initialized busses and ioremap the requested memory range
  46. */
  47. void iop13xx_map_pci_memory(void)
  48. {
  49. int atu;
  50. struct pci_bus *bus;
  51. struct pci_dev *dev;
  52. resource_size_t end = 0;
  53. for (atu = 0; atu < 2; atu++) {
  54. bus = atu ? pci_bus_atue : pci_bus_atux;
  55. if (bus) {
  56. list_for_each_entry(dev, &bus->devices, bus_list) {
  57. int i;
  58. int max = 7;
  59. if (dev->subordinate)
  60. max = DEVICE_COUNT_RESOURCE;
  61. for (i = 0; i < max; i++) {
  62. struct resource *res = &dev->resource[i];
  63. if (res->flags & IORESOURCE_MEM)
  64. end = max(res->end, end);
  65. }
  66. }
  67. switch(atu) {
  68. case 0:
  69. iop13xx_atux_mem_size =
  70. (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;
  71. /* 16MB align the request */
  72. if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
  73. iop13xx_atux_mem_size &= ~(SZ_16M - 1);
  74. iop13xx_atux_mem_size += SZ_16M;
  75. }
  76. if (end) {
  77. iop13xx_atux_mem_base =
  78. (u32) __ioremap_pfn(
  79. __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
  80. , 0, iop13xx_atux_mem_size, 0);
  81. if (!iop13xx_atux_mem_base) {
  82. printk("%s: atux allocation "
  83. "failed\n", __FUNCTION__);
  84. BUG();
  85. }
  86. } else
  87. iop13xx_atux_mem_size = 0;
  88. PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
  89. __FUNCTION__, atu, iop13xx_atux_mem_size,
  90. iop13xx_atux_mem_base);
  91. break;
  92. case 1:
  93. iop13xx_atue_mem_size =
  94. (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;
  95. /* 16MB align the request */
  96. if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
  97. iop13xx_atue_mem_size &= ~(SZ_16M - 1);
  98. iop13xx_atue_mem_size += SZ_16M;
  99. }
  100. if (end) {
  101. iop13xx_atue_mem_base =
  102. (u32) __ioremap_pfn(
  103. __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
  104. , 0, iop13xx_atue_mem_size, 0);
  105. if (!iop13xx_atue_mem_base) {
  106. printk("%s: atue allocation "
  107. "failed\n", __FUNCTION__);
  108. BUG();
  109. }
  110. } else
  111. iop13xx_atue_mem_size = 0;
  112. PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
  113. __FUNCTION__, atu, iop13xx_atue_mem_size,
  114. iop13xx_atue_mem_base);
  115. break;
  116. }
  117. printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
  118. atu ? "ATUE" : "ATUX",
  119. (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
  120. SZ_1M,
  121. atu ? IOP13XX_PCIE_LOWER_MEM_RA :
  122. IOP13XX_PCIX_LOWER_MEM_RA,
  123. atu ? iop13xx_atue_mem_base :
  124. iop13xx_atux_mem_base);
  125. end = 0;
  126. }
  127. }
  128. }
  129. static inline int iop13xx_atu_function(int atu)
  130. {
  131. int func = 0;
  132. /* the function number depends on the value of the
  133. * IOP13XX_INTERFACE_SEL_PCIX reset strap
  134. * see C-Spec section 3.17
  135. */
  136. switch(atu) {
  137. case IOP13XX_INIT_ATU_ATUX:
  138. if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
  139. func = 5;
  140. else
  141. func = 0;
  142. break;
  143. case IOP13XX_INIT_ATU_ATUE:
  144. if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
  145. func = 0;
  146. else
  147. func = 5;
  148. break;
  149. default:
  150. BUG();
  151. }
  152. return func;
  153. }
  154. /* iop13xx_atux_cfg_address - format a configuration address for atux
  155. * @bus: Target bus to access
  156. * @devfn: Combined device number and function number
  157. * @where: Desired register's address offset
  158. *
  159. * Convert the parameters to a configuration address formatted
  160. * according the PCI-X 2.0 specification
  161. */
  162. static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
  163. {
  164. struct pci_sys_data *sys = bus->sysdata;
  165. u32 addr;
  166. if (sys->busnr == bus->number)
  167. addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
  168. else
  169. addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
  170. addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
  171. addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */
  172. return addr;
  173. }
  174. /* iop13xx_atue_cfg_address - format a configuration address for atue
  175. * @bus: Target bus to access
  176. * @devfn: Combined device number and function number
  177. * @where: Desired register's address offset
  178. *
  179. * Convert the parameters to an address usable by the ATUE_OCCAR
  180. */
  181. static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
  182. {
  183. struct pci_sys_data *sys = bus->sysdata;
  184. u32 addr;
  185. PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
  186. bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
  187. addr = ((u32) bus->number) << IOP13XX_ATUE_OCCAR_BUS_NUM |
  188. ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
  189. ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
  190. (where & ~0x3);
  191. if (sys->busnr != bus->number)
  192. addr |= 1; /* type 1 access */
  193. return addr;
  194. }
  195. /* This routine checks the status of the last configuration cycle. If an error
  196. * was detected it returns >0, else it returns a 0. The errors being checked
  197. * are parity, master abort, target abort (master and target). These types of
  198. * errors occure during a config cycle where there is no device, like during
  199. * the discovery stage.
  200. */
  201. static int iop13xx_atux_pci_status(int clear)
  202. {
  203. unsigned int status;
  204. int err = 0;
  205. /*
  206. * Check the status registers.
  207. */
  208. status = __raw_readw(IOP13XX_ATUX_ATUSR);
  209. if (status & IOP_PCI_STATUS_ERROR)
  210. {
  211. PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
  212. if(clear)
  213. __raw_writew(status & IOP_PCI_STATUS_ERROR,
  214. IOP13XX_ATUX_ATUSR);
  215. err = 1;
  216. }
  217. status = __raw_readl(IOP13XX_ATUX_ATUISR);
  218. if (status & IOP13XX_ATUX_ATUISR_ERROR)
  219. {
  220. PRINTK("\t\t\tPCI error interrupt: ATUISR %#08x", status);
  221. if(clear)
  222. __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
  223. IOP13XX_ATUX_ATUISR);
  224. err = 1;
  225. }
  226. return err;
  227. }
  228. /* Simply write the address register and read the configuration
  229. * data. Note that the data dependency on %0 encourages an abort
  230. * to be detected before we return.
  231. */
  232. static inline u32 iop13xx_atux_read(unsigned long addr)
  233. {
  234. u32 val;
  235. __asm__ __volatile__(
  236. "str %1, [%2]\n\t"
  237. "ldr %0, [%3]\n\t"
  238. "mov %0, %0\n\t"
  239. : "=r" (val)
  240. : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));
  241. return val;
  242. }
  243. /* The read routines must check the error status of the last configuration
  244. * cycle. If there was an error, the routine returns all hex f's.
  245. */
  246. static int
  247. iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  248. int size, u32 *value)
  249. {
  250. unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
  251. u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);
  252. if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
  253. __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
  254. IOP13XX_XBG_BECSR);
  255. val = 0xffffffff;
  256. }
  257. *value = val;
  258. return PCIBIOS_SUCCESSFUL;
  259. }
  260. static int
  261. iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
  262. int size, u32 value)
  263. {
  264. unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
  265. u32 val;
  266. if (size != 4) {
  267. val = iop13xx_atux_read(addr);
  268. if (!iop13xx_atux_pci_status(1) == 0)
  269. return PCIBIOS_SUCCESSFUL;
  270. where = (where & 3) * 8;
  271. if (size == 1)
  272. val &= ~(0xff << where);
  273. else
  274. val &= ~(0xffff << where);
  275. __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
  276. } else {
  277. __raw_writel(addr, IOP13XX_ATUX_OCCAR);
  278. __raw_writel(value, IOP13XX_ATUX_OCCDR);
  279. }
  280. return PCIBIOS_SUCCESSFUL;
  281. }
  282. static struct pci_ops iop13xx_atux_ops = {
  283. .read = iop13xx_atux_read_config,
  284. .write = iop13xx_atux_write_config,
  285. };
  286. /* This routine checks the status of the last configuration cycle. If an error
  287. * was detected it returns >0, else it returns a 0. The errors being checked
  288. * are parity, master abort, target abort (master and target). These types of
  289. * errors occure during a config cycle where there is no device, like during
  290. * the discovery stage.
  291. */
  292. static int iop13xx_atue_pci_status(int clear)
  293. {
  294. unsigned int status;
  295. int err = 0;
  296. /*
  297. * Check the status registers.
  298. */
  299. /* standard pci status register */
  300. status = __raw_readw(IOP13XX_ATUE_ATUSR);
  301. if (status & IOP_PCI_STATUS_ERROR) {
  302. PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
  303. if(clear)
  304. __raw_writew(status & IOP_PCI_STATUS_ERROR,
  305. IOP13XX_ATUE_ATUSR);
  306. err++;
  307. }
  308. /* check the normal status bits in the ATUISR */
  309. status = __raw_readl(IOP13XX_ATUE_ATUISR);
  310. if (status & IOP13XX_ATUE_ATUISR_ERROR) {
  311. PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
  312. if (clear)
  313. __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
  314. IOP13XX_ATUE_ATUISR);
  315. err++;
  316. /* check the PCI-E status if the ATUISR reports an interface error */
  317. if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
  318. /* get the unmasked errors */
  319. status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
  320. ~(__raw_readl(IOP13XX_ATUE_PIE_MSK));
  321. if (status) {
  322. PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
  323. __raw_readl(IOP13XX_ATUE_PIE_STS));
  324. err++;
  325. } else {
  326. PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
  327. __raw_readl(IOP13XX_ATUE_PIE_STS));
  328. PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
  329. __raw_readl(IOP13XX_ATUE_PIE_MSK));
  330. BUG();
  331. }
  332. if(clear)
  333. __raw_writel(status, IOP13XX_ATUE_PIE_STS);
  334. }
  335. }
  336. return err;
  337. }
  338. static inline int __init
  339. iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
  340. {
  341. WARN_ON(idsel != 0);
  342. switch (pin) {
  343. case 1: return ATUE_INTA;
  344. case 2: return ATUE_INTB;
  345. case 3: return ATUE_INTC;
  346. case 4: return ATUE_INTD;
  347. default: return -1;
  348. }
  349. }
  350. static inline u32 iop13xx_atue_read(unsigned long addr)
  351. {
  352. u32 val;
  353. __raw_writel(addr, IOP13XX_ATUE_OCCAR);
  354. val = __raw_readl(IOP13XX_ATUE_OCCDR);
  355. rmb();
  356. return val;
  357. }
  358. /* The read routines must check the error status of the last configuration
  359. * cycle. If there was an error, the routine returns all hex f's.
  360. */
  361. static int
  362. iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  363. int size, u32 *value)
  364. {
  365. u32 val;
  366. unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
  367. /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
  368. if (!PCI_SLOT(devfn) || (addr & 1)) {
  369. val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
  370. if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
  371. __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
  372. IOP13XX_XBG_BECSR);
  373. val = 0xffffffff;
  374. }
  375. PRINTK("addr=%#0lx, val=%#010x", addr, val);
  376. } else
  377. val = 0xffffffff;
  378. *value = val;
  379. return PCIBIOS_SUCCESSFUL;
  380. }
  381. static int
  382. iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
  383. int size, u32 value)
  384. {
  385. unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
  386. u32 val;
  387. if (size != 4) {
  388. val = iop13xx_atue_read(addr);
  389. if (!iop13xx_atue_pci_status(1) == 0)
  390. return PCIBIOS_SUCCESSFUL;
  391. where = (where & 3) * 8;
  392. if (size == 1)
  393. val &= ~(0xff << where);
  394. else
  395. val &= ~(0xffff << where);
  396. __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
  397. } else {
  398. __raw_writel(addr, IOP13XX_ATUE_OCCAR);
  399. __raw_writel(value, IOP13XX_ATUE_OCCDR);
  400. }
  401. return PCIBIOS_SUCCESSFUL;
  402. }
  403. static struct pci_ops iop13xx_atue_ops = {
  404. .read = iop13xx_atue_read_config,
  405. .write = iop13xx_atue_write_config,
  406. };
  407. /* When a PCI device does not exist during config cycles, the XScale gets a
  408. * bus error instead of returning 0xffffffff. We can't rely on the ATU status
  409. * bits to tell us that it was indeed a configuration cycle that caused this
  410. * error especially in the case when the ATUE link is down. Instead we rely
  411. * on data from the south XSI bridge to validate the abort
  412. */
  413. int
  414. iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
  415. {
  416. PRINTK("Data abort: address = 0x%08lx "
  417. "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
  418. addr, fsr, regs->ARM_pc, regs->ARM_lr);
  419. PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
  420. PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
  421. PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));
  422. /* If it was an imprecise abort, then we need to correct the
  423. * return address to be _after_ the instruction.
  424. */
  425. if (fsr & (1 << 10))
  426. regs->ARM_pc += 4;
  427. if (is_atue_occdr_error() || is_atux_occdr_error())
  428. return 0;
  429. else
  430. return 1;
  431. }
  432. /* Scan an IOP13XX PCI bus. nr selects which ATU we use.
  433. */
  434. struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
  435. {
  436. int which_atu;
  437. struct pci_bus *bus = NULL;
  438. switch (init_atu) {
  439. case IOP13XX_INIT_ATU_ATUX:
  440. which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
  441. break;
  442. case IOP13XX_INIT_ATU_ATUE:
  443. which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
  444. break;
  445. case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
  446. which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
  447. break;
  448. default:
  449. which_atu = 0;
  450. }
  451. if (!which_atu) {
  452. BUG();
  453. return NULL;
  454. }
  455. switch (which_atu) {
  456. case IOP13XX_INIT_ATU_ATUX:
  457. if (time_after_eq(jiffies + msecs_to_jiffies(1000),
  458. atux_trhfa_timeout)) /* ensure not wrap */
  459. while(time_before(jiffies, atux_trhfa_timeout))
  460. udelay(100);
  461. bus = pci_bus_atux = pci_scan_bus(sys->busnr,
  462. &iop13xx_atux_ops,
  463. sys);
  464. break;
  465. case IOP13XX_INIT_ATU_ATUE:
  466. bus = pci_bus_atue = pci_scan_bus(sys->busnr,
  467. &iop13xx_atue_ops,
  468. sys);
  469. break;
  470. }
  471. return bus;
  472. }
  473. /* This function is called from iop13xx_pci_init() after assigning valid
  474. * values to iop13xx_atue_pmmr_offset. This is the location for common
  475. * setup of ATUE for all IOP13XX implementations.
  476. */
  477. void __init iop13xx_atue_setup(void)
  478. {
  479. int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
  480. u32 reg_val;
  481. /* BAR 1 (1:1 mapping with Physical RAM) */
  482. /* Set limit and enable */
  483. __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
  484. IOP13XX_ATUE_IALR1);
  485. __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
  486. /* Set base at the top of the reserved address space */
  487. __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
  488. PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);
  489. /* 1:1 mapping with physical ram
  490. * (leave big endian byte swap disabled)
  491. */
  492. __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
  493. __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
  494. /* Outbound window 1 (PCIX/PCIE memory window) */
  495. /* 32 bit Address Space */
  496. __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
  497. /* PA[35:32] */
  498. __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
  499. (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
  500. IOP13XX_ATUE_OUMBAR1);
  501. /* Setup the I/O Bar
  502. * A[35-16] in 31-12
  503. */
  504. __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
  505. IOP13XX_ATUE_OIOBAR);
  506. __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
  507. /* clear startup errors */
  508. iop13xx_atue_pci_status(1);
  509. /* OIOBAR function number
  510. */
  511. reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
  512. reg_val &= ~0x7;
  513. reg_val |= func;
  514. __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
  515. /* OUMBAR function numbers
  516. */
  517. reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
  518. reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
  519. IOP13XX_ATU_OUMBAR_FUNC_NUM);
  520. reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
  521. __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
  522. reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
  523. reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
  524. IOP13XX_ATU_OUMBAR_FUNC_NUM);
  525. reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
  526. __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
  527. reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
  528. reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
  529. IOP13XX_ATU_OUMBAR_FUNC_NUM);
  530. reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
  531. __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
  532. reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
  533. reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
  534. IOP13XX_ATU_OUMBAR_FUNC_NUM);
  535. reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
  536. __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
  537. /* Enable inbound and outbound cycles
  538. */
  539. reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
  540. reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  541. PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  542. __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
  543. reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
  544. reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
  545. IOP13XX_ATUE_ATUCR_IVM;
  546. __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
  547. }
  548. void __init iop13xx_atue_disable(void)
  549. {
  550. u32 reg_val;
  551. __raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
  552. __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);
  553. /* wait for cycles to quiesce */
  554. while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
  555. IOP13XX_ATUE_PCSR_IN_Q_BUSY |
  556. IOP13XX_ATUE_PCSR_LLRB_BUSY))
  557. cpu_relax();
  558. /* BAR 0 ( Disabled ) */
  559. __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
  560. __raw_writel(0x0, IOP13XX_ATUE_IABAR0);
  561. __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
  562. __raw_writel(0x0, IOP13XX_ATUE_IATVR0);
  563. __raw_writel(0x0, IOP13XX_ATUE_IALR0);
  564. reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
  565. reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
  566. __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
  567. /* BAR 1 ( Disabled ) */
  568. __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
  569. __raw_writel(0x0, IOP13XX_ATUE_IABAR1);
  570. __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
  571. __raw_writel(0x0, IOP13XX_ATUE_IATVR1);
  572. __raw_writel(0x0, IOP13XX_ATUE_IALR1);
  573. reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
  574. reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
  575. __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
  576. /* BAR 2 ( Disabled ) */
  577. __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
  578. __raw_writel(0x0, IOP13XX_ATUE_IABAR2);
  579. __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
  580. __raw_writel(0x0, IOP13XX_ATUE_IATVR2);
  581. __raw_writel(0x0, IOP13XX_ATUE_IALR2);
  582. reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
  583. reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
  584. __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
  585. /* BAR 3 ( Disabled ) */
  586. reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
  587. reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
  588. __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
  589. /* Setup the I/O Bar
  590. * A[35-16] in 31-12
  591. */
  592. __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
  593. IOP13XX_ATUE_OIOBAR);
  594. __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
  595. }
  596. /* This function is called from iop13xx_pci_init() after assigning valid
  597. * values to iop13xx_atux_pmmr_offset. This is the location for common
  598. * setup of ATUX for all IOP13XX implementations.
  599. */
  600. void __init iop13xx_atux_setup(void)
  601. {
  602. u32 reg_val;
  603. int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);
  604. /* Take PCI-X bus out of reset if bootloader hasn't already.
  605. * According to spec, we should wait for 2^25 PCI clocks to meet
  606. * the PCI timing parameter Trhfa (RST# high to first access).
  607. * This is rarely necessary and often ignored.
  608. */
  609. reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
  610. if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
  611. int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
  612. msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */
  613. __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
  614. IOP13XX_ATUX_PCSR);
  615. atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
  616. }
  617. else
  618. atux_trhfa_timeout = jiffies;
  619. /* BAR 1 (1:1 mapping with Physical RAM) */
  620. /* Set limit and enable */
  621. __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
  622. IOP13XX_ATUX_IALR1);
  623. __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
  624. /* Set base at the top of the reserved address space */
  625. __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
  626. PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);
  627. /* 1:1 mapping with physical ram
  628. * (leave big endian byte swap disabled)
  629. */
  630. __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
  631. __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
  632. /* Outbound window 1 (PCIX/PCIE memory window) */
  633. /* 32 bit Address Space */
  634. __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
  635. /* PA[35:32] */
  636. __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
  637. IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
  638. IOP13XX_ATUX_OUMBAR1);
  639. /* Setup the I/O Bar
  640. * A[35-16] in 31-12
  641. */
  642. __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
  643. IOP13XX_ATUX_OIOBAR);
  644. __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
  645. /* clear startup errors */
  646. iop13xx_atux_pci_status(1);
  647. /* OIOBAR function number
  648. */
  649. reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
  650. reg_val &= ~0x7;
  651. reg_val |= func;
  652. __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
  653. /* OUMBAR function numbers
  654. */
  655. reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
  656. reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
  657. IOP13XX_ATU_OUMBAR_FUNC_NUM);
  658. reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
  659. __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
  660. reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
  661. reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
  662. IOP13XX_ATU_OUMBAR_FUNC_NUM);
  663. reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
  664. __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
  665. reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
  666. reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
  667. IOP13XX_ATU_OUMBAR_FUNC_NUM);
  668. reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
  669. __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
  670. reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
  671. reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
  672. IOP13XX_ATU_OUMBAR_FUNC_NUM);
  673. reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
  674. __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
  675. /* Enable inbound and outbound cycles
  676. */
  677. reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
  678. reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  679. PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  680. __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
  681. reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
  682. reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
  683. __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
  684. }
  685. void __init iop13xx_atux_disable(void)
  686. {
  687. u32 reg_val;
  688. __raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
  689. __raw_writel(0x0, IOP13XX_ATUX_ATUCR);
  690. /* wait for cycles to quiesce */
  691. while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
  692. IOP13XX_ATUX_PCSR_IN_Q_BUSY))
  693. cpu_relax();
  694. /* BAR 0 ( Disabled ) */
  695. __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
  696. __raw_writel(0x0, IOP13XX_ATUX_IABAR0);
  697. __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
  698. __raw_writel(0x0, IOP13XX_ATUX_IATVR0);
  699. __raw_writel(0x0, IOP13XX_ATUX_IALR0);
  700. reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
  701. reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
  702. __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
  703. /* BAR 1 ( Disabled ) */
  704. __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
  705. __raw_writel(0x0, IOP13XX_ATUX_IABAR1);
  706. __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
  707. __raw_writel(0x0, IOP13XX_ATUX_IATVR1);
  708. __raw_writel(0x0, IOP13XX_ATUX_IALR1);
  709. reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
  710. reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
  711. __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
  712. /* BAR 2 ( Disabled ) */
  713. __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
  714. __raw_writel(0x0, IOP13XX_ATUX_IABAR2);
  715. __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
  716. __raw_writel(0x0, IOP13XX_ATUX_IATVR2);
  717. __raw_writel(0x0, IOP13XX_ATUX_IALR2);
  718. reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
  719. reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
  720. __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
  721. /* BAR 3 ( Disabled ) */
  722. __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
  723. __raw_writel(0x0, IOP13XX_ATUX_IABAR3);
  724. __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
  725. __raw_writel(0x0, IOP13XX_ATUX_IATVR3);
  726. __raw_writel(0x0, IOP13XX_ATUX_IALR3);
  727. reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
  728. reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
  729. __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
  730. /* Setup the I/O Bar
  731. * A[35-16] in 31-12
  732. */
  733. __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
  734. IOP13XX_ATUX_OIOBAR);
  735. __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
  736. }
  737. void __init iop13xx_set_atu_mmr_bases(void)
  738. {
  739. /* Based on ESSR0, determine the ATU X/E offsets */
  740. switch(__raw_readl(IOP13XX_ESSR0) &
  741. (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
  742. /* both asserted */
  743. case 0:
  744. iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
  745. iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
  746. break;
  747. /* IOP13XX_CONTROLLER_ONLY = deasserted
  748. * IOP13XX_INTERFACE_SEL_PCIX = asserted
  749. */
  750. case IOP13XX_CONTROLLER_ONLY:
  751. iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
  752. iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
  753. break;
  754. /* IOP13XX_CONTROLLER_ONLY = asserted
  755. * IOP13XX_INTERFACE_SEL_PCIX = deasserted
  756. */
  757. case IOP13XX_INTERFACE_SEL_PCIX:
  758. iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
  759. iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
  760. break;
  761. /* both deasserted */
  762. case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
  763. iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
  764. iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
  765. break;
  766. default:
  767. BUG();
  768. }
  769. }
  770. void __init iop13xx_atu_select(struct hw_pci *plat_pci)
  771. {
  772. int i;
  773. /* set system defaults
  774. * note: if "iop13xx_init_atu=" is specified this autodetect
  775. * sequence will be bypassed
  776. */
  777. if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
  778. /* check for single/dual interface */
  779. if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
  780. /* ATUE must be present check the device id
  781. * to see if ATUX is present.
  782. */
  783. init_atu |= IOP13XX_INIT_ATU_ATUE;
  784. switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
  785. case 0x70:
  786. case 0x80:
  787. case 0xc0:
  788. init_atu |= IOP13XX_INIT_ATU_ATUX;
  789. break;
  790. }
  791. } else {
  792. /* ATUX must be present check the device id
  793. * to see if ATUE is present.
  794. */
  795. init_atu |= IOP13XX_INIT_ATU_ATUX;
  796. switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
  797. case 0x70:
  798. case 0x80:
  799. case 0xc0:
  800. init_atu |= IOP13XX_INIT_ATU_ATUE;
  801. break;
  802. }
  803. }
  804. /* check central resource and root complex capability */
  805. if (init_atu & IOP13XX_INIT_ATU_ATUX)
  806. if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
  807. IOP13XX_ATUX_PCSR_CENTRAL_RES))
  808. init_atu &= ~IOP13XX_INIT_ATU_ATUX;
  809. if (init_atu & IOP13XX_INIT_ATU_ATUE)
  810. if (__raw_readl(IOP13XX_ATUE_PCSR) &
  811. IOP13XX_ATUE_PCSR_END_POINT)
  812. init_atu &= ~IOP13XX_INIT_ATU_ATUE;
  813. }
  814. for (i = 0; i < 2; i++) {
  815. if((init_atu & (1 << i)) == (1 << i))
  816. plat_pci->nr_controllers++;
  817. }
  818. }
  819. void __init iop13xx_pci_init(void)
  820. {
  821. /* clear pre-existing south bridge errors */
  822. __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
  823. /* Setup the Min Address for PCI memory... */
  824. iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
  825. /* if Linux is given control of an ATU
  826. * clear out its prior configuration,
  827. * otherwise do not touch the registers
  828. */
  829. if (init_atu & IOP13XX_INIT_ATU_ATUE) {
  830. iop13xx_atue_disable();
  831. iop13xx_atue_setup();
  832. }
  833. if (init_atu & IOP13XX_INIT_ATU_ATUX) {
  834. iop13xx_atux_disable();
  835. iop13xx_atux_setup();
  836. }
  837. hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS,
  838. "imprecise external abort");
  839. }
  840. /* intialize the pci memory space. handle any combination of
  841. * atue and atux enabled/disabled
  842. */
  843. int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
  844. {
  845. struct resource *res;
  846. int which_atu;
  847. u32 pcixsr, pcsr;
  848. if (nr > 1)
  849. return 0;
  850. res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
  851. if (!res)
  852. panic("PCI: unable to alloc resources");
  853. memset(res, 0, sizeof(struct resource) * 2);
  854. /* 'nr' assumptions:
  855. * ATUX is always 0
  856. * ATUE is 1 when ATUX is also enabled
  857. * ATUE is 0 when ATUX is disabled
  858. */
  859. switch(init_atu) {
  860. case IOP13XX_INIT_ATU_ATUX:
  861. which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
  862. break;
  863. case IOP13XX_INIT_ATU_ATUE:
  864. which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
  865. break;
  866. case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
  867. which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
  868. break;
  869. default:
  870. which_atu = 0;
  871. }
  872. if (!which_atu)
  873. return 0;
  874. switch(which_atu) {
  875. case IOP13XX_INIT_ATU_ATUX:
  876. pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
  877. pcixsr &= ~0xffff;
  878. pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
  879. 0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
  880. iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
  881. << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
  882. __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
  883. res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET;
  884. res[0].end = IOP13XX_PCIX_UPPER_IO_PA;
  885. res[0].name = "IQ81340 ATUX PCI I/O Space";
  886. res[0].flags = IORESOURCE_IO;
  887. res[1].start = IOP13XX_PCIX_LOWER_MEM_RA;
  888. res[1].end = IOP13XX_PCIX_UPPER_MEM_RA;
  889. res[1].name = "IQ81340 ATUX PCI Memory Space";
  890. res[1].flags = IORESOURCE_MEM;
  891. sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
  892. sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
  893. break;
  894. case IOP13XX_INIT_ATU_ATUE:
  895. /* Note: the function number field in the PCSR is ro */
  896. pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
  897. pcsr &= ~(0xfff8 << 16);
  898. pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
  899. 0 << IOP13XX_ATUE_PCSR_DEV_NUM;
  900. __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
  901. res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET;
  902. res[0].end = IOP13XX_PCIE_UPPER_IO_PA;
  903. res[0].name = "IQ81340 ATUE PCI I/O Space";
  904. res[0].flags = IORESOURCE_IO;
  905. res[1].start = IOP13XX_PCIE_LOWER_MEM_RA;
  906. res[1].end = IOP13XX_PCIE_UPPER_MEM_RA;
  907. res[1].name = "IQ81340 ATUE PCI Memory Space";
  908. res[1].flags = IORESOURCE_MEM;
  909. sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
  910. sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
  911. sys->map_irq = iop13xx_pcie_map_irq;
  912. break;
  913. default:
  914. return 0;
  915. }
  916. request_resource(&ioport_resource, &res[0]);
  917. request_resource(&iomem_resource, &res[1]);
  918. sys->resource[0] = &res[0];
  919. sys->resource[1] = &res[1];
  920. sys->resource[2] = NULL;
  921. return 1;
  922. }
  923. u16 iop13xx_dev_id(void)
  924. {
  925. if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
  926. return __raw_readw(IOP13XX_ATUE_DID);
  927. else
  928. return __raw_readw(IOP13XX_ATUX_DID);
  929. }
  930. static int __init iop13xx_init_atu_setup(char *str)
  931. {
  932. init_atu = IOP13XX_INIT_ATU_NONE;
  933. if (str) {
  934. while (*str != '\0') {
  935. switch (*str) {
  936. case 'x':
  937. case 'X':
  938. init_atu |= IOP13XX_INIT_ATU_ATUX;
  939. init_atu &= ~IOP13XX_INIT_ATU_NONE;
  940. break;
  941. case 'e':
  942. case 'E':
  943. init_atu |= IOP13XX_INIT_ATU_ATUE;
  944. init_atu &= ~IOP13XX_INIT_ATU_NONE;
  945. break;
  946. case ',':
  947. case '=':
  948. break;
  949. default:
  950. PRINTK("\"iop13xx_init_atu\" malformed at "
  951. "character: \'%c\'", *str);
  952. *(str + 1) = '\0';
  953. init_atu = IOP13XX_INIT_ATU_DEFAULT;
  954. }
  955. str++;
  956. }
  957. }
  958. return 1;
  959. }
  960. __setup("iop13xx_init_atu", iop13xx_init_atu_setup);