irq.c 5.7 KB

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  1. /*
  2. * iop13xx IRQ handling / support functions
  3. * Copyright (c) 2005-2006, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  16. * Place - Suite 330, Boston, MA 02111-1307 USA.
  17. *
  18. */
  19. #include <linux/init.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/list.h>
  22. #include <linux/sysctl.h>
  23. #include <asm/uaccess.h>
  24. #include <asm/mach/irq.h>
  25. #include <asm/irq.h>
  26. #include <asm/hardware.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/arch/irqs.h>
  29. /* INTCTL0 CP6 R0 Page 4
  30. */
  31. static inline u32 read_intctl_0(void)
  32. {
  33. u32 val;
  34. asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
  35. return val;
  36. }
  37. static inline void write_intctl_0(u32 val)
  38. {
  39. asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
  40. }
  41. /* INTCTL1 CP6 R1 Page 4
  42. */
  43. static inline u32 read_intctl_1(void)
  44. {
  45. u32 val;
  46. asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
  47. return val;
  48. }
  49. static inline void write_intctl_1(u32 val)
  50. {
  51. asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
  52. }
  53. /* INTCTL2 CP6 R2 Page 4
  54. */
  55. static inline u32 read_intctl_2(void)
  56. {
  57. u32 val;
  58. asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
  59. return val;
  60. }
  61. static inline void write_intctl_2(u32 val)
  62. {
  63. asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
  64. }
  65. /* INTCTL3 CP6 R3 Page 4
  66. */
  67. static inline u32 read_intctl_3(void)
  68. {
  69. u32 val;
  70. asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
  71. return val;
  72. }
  73. static inline void write_intctl_3(u32 val)
  74. {
  75. asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
  76. }
  77. /* INTSTR0 CP6 R0 Page 5
  78. */
  79. static inline u32 read_intstr_0(void)
  80. {
  81. u32 val;
  82. asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
  83. return val;
  84. }
  85. static inline void write_intstr_0(u32 val)
  86. {
  87. asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
  88. }
  89. /* INTSTR1 CP6 R1 Page 5
  90. */
  91. static inline u32 read_intstr_1(void)
  92. {
  93. u32 val;
  94. asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
  95. return val;
  96. }
  97. static void write_intstr_1(u32 val)
  98. {
  99. asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
  100. }
  101. /* INTSTR2 CP6 R2 Page 5
  102. */
  103. static inline u32 read_intstr_2(void)
  104. {
  105. u32 val;
  106. asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
  107. return val;
  108. }
  109. static void write_intstr_2(u32 val)
  110. {
  111. asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
  112. }
  113. /* INTSTR3 CP6 R3 Page 5
  114. */
  115. static inline u32 read_intstr_3(void)
  116. {
  117. u32 val;
  118. asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
  119. return val;
  120. }
  121. static void write_intstr_3(u32 val)
  122. {
  123. asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
  124. }
  125. /* INTBASE CP6 R0 Page 2
  126. */
  127. static inline u32 read_intbase(void)
  128. {
  129. u32 val;
  130. asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
  131. return val;
  132. }
  133. static void write_intbase(u32 val)
  134. {
  135. asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
  136. }
  137. /* INTSIZE CP6 R2 Page 2
  138. */
  139. static inline u32 read_intsize(void)
  140. {
  141. u32 val;
  142. asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
  143. return val;
  144. }
  145. static void write_intsize(u32 val)
  146. {
  147. asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
  148. }
  149. /* 0 = Interrupt Masked and 1 = Interrupt not masked */
  150. static void
  151. iop13xx_irq_mask0 (unsigned int irq)
  152. {
  153. write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
  154. }
  155. static void
  156. iop13xx_irq_mask1 (unsigned int irq)
  157. {
  158. write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
  159. }
  160. static void
  161. iop13xx_irq_mask2 (unsigned int irq)
  162. {
  163. write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
  164. }
  165. static void
  166. iop13xx_irq_mask3 (unsigned int irq)
  167. {
  168. write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
  169. }
  170. static void
  171. iop13xx_irq_unmask0(unsigned int irq)
  172. {
  173. write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
  174. }
  175. static void
  176. iop13xx_irq_unmask1(unsigned int irq)
  177. {
  178. write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
  179. }
  180. static void
  181. iop13xx_irq_unmask2(unsigned int irq)
  182. {
  183. write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
  184. }
  185. static void
  186. iop13xx_irq_unmask3(unsigned int irq)
  187. {
  188. write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
  189. }
  190. static struct irq_chip iop13xx_irqchip1 = {
  191. .name = "IOP13xx-1",
  192. .ack = iop13xx_irq_mask0,
  193. .mask = iop13xx_irq_mask0,
  194. .unmask = iop13xx_irq_unmask0,
  195. };
  196. static struct irq_chip iop13xx_irqchip2 = {
  197. .name = "IOP13xx-2",
  198. .ack = iop13xx_irq_mask1,
  199. .mask = iop13xx_irq_mask1,
  200. .unmask = iop13xx_irq_unmask1,
  201. };
  202. static struct irq_chip iop13xx_irqchip3 = {
  203. .name = "IOP13xx-3",
  204. .ack = iop13xx_irq_mask2,
  205. .mask = iop13xx_irq_mask2,
  206. .unmask = iop13xx_irq_unmask2,
  207. };
  208. static struct irq_chip iop13xx_irqchip4 = {
  209. .name = "IOP13xx-4",
  210. .ack = iop13xx_irq_mask3,
  211. .mask = iop13xx_irq_mask3,
  212. .unmask = iop13xx_irq_unmask3,
  213. };
  214. extern void iop_init_cp6_handler(void);
  215. void __init iop13xx_init_irq(void)
  216. {
  217. unsigned int i;
  218. iop_init_cp6_handler();
  219. /* disable all interrupts */
  220. write_intctl_0(0);
  221. write_intctl_1(0);
  222. write_intctl_2(0);
  223. write_intctl_3(0);
  224. /* treat all as IRQ */
  225. write_intstr_0(0);
  226. write_intstr_1(0);
  227. write_intstr_2(0);
  228. write_intstr_3(0);
  229. /* initialize the interrupt vector generator */
  230. write_intbase(INTBASE);
  231. write_intsize(INTSIZE_4);
  232. for(i = 0; i < NR_IOP13XX_IRQS; i++) {
  233. if (i < 32)
  234. set_irq_chip(i, &iop13xx_irqchip1);
  235. else if (i < 64)
  236. set_irq_chip(i, &iop13xx_irqchip2);
  237. else if (i < 96)
  238. set_irq_chip(i, &iop13xx_irqchip3);
  239. else
  240. set_irq_chip(i, &iop13xx_irqchip4);
  241. set_irq_handler(i, handle_level_irq);
  242. set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
  243. }
  244. }