irq.c 5.9 KB

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  1. /*
  2. * linux/arch/arm/mach-imx/irq.c
  3. *
  4. * Copyright (C) 1999 ARM Limited
  5. * Copyright (C) 2002 Shane Nay (shane@minirl.com)
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. *
  21. * 03/03/2004 Sascha Hauer <sascha@saschahauer.de>
  22. * Copied from the motorola bsp package and added gpio demux
  23. * interrupt handler
  24. */
  25. #include <linux/init.h>
  26. #include <linux/list.h>
  27. #include <linux/timer.h>
  28. #include <asm/hardware.h>
  29. #include <asm/irq.h>
  30. #include <asm/io.h>
  31. #include <asm/mach/irq.h>
  32. /*
  33. *
  34. * We simply use the ENABLE DISABLE registers inside of the IMX
  35. * to turn on/off specific interrupts. FIXME- We should
  36. * also add support for the accelerated interrupt controller
  37. * by putting offets to irq jump code in the appropriate
  38. * places.
  39. *
  40. */
  41. #define INTENNUM_OFF 0x8
  42. #define INTDISNUM_OFF 0xC
  43. #define VA_AITC_BASE IO_ADDRESS(IMX_AITC_BASE)
  44. #define IMX_AITC_INTDISNUM (VA_AITC_BASE + INTDISNUM_OFF)
  45. #define IMX_AITC_INTENNUM (VA_AITC_BASE + INTENNUM_OFF)
  46. #if 0
  47. #define DEBUG_IRQ(fmt...) printk(fmt)
  48. #else
  49. #define DEBUG_IRQ(fmt...) do { } while (0)
  50. #endif
  51. static void
  52. imx_mask_irq(unsigned int irq)
  53. {
  54. __raw_writel(irq, IMX_AITC_INTDISNUM);
  55. }
  56. static void
  57. imx_unmask_irq(unsigned int irq)
  58. {
  59. __raw_writel(irq, IMX_AITC_INTENNUM);
  60. }
  61. static int
  62. imx_gpio_irq_type(unsigned int _irq, unsigned int type)
  63. {
  64. unsigned int irq_type = 0, irq, reg, bit;
  65. irq = _irq - IRQ_GPIOA(0);
  66. reg = irq >> 5;
  67. bit = 1 << (irq % 32);
  68. if (type == IRQT_PROBE) {
  69. /* Don't mess with enabled GPIOs using preconfigured edges or
  70. GPIOs set to alternate function during probe */
  71. /* TODO: support probe */
  72. // if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) &
  73. // GPIO_bit(gpio))
  74. // return 0;
  75. // if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
  76. // return 0;
  77. // type = __IRQT_RISEDGE | __IRQT_FALEDGE;
  78. }
  79. GIUS(reg) |= bit;
  80. DDIR(reg) &= ~(bit);
  81. DEBUG_IRQ("setting type of irq %d to ", _irq);
  82. if (type & __IRQT_RISEDGE) {
  83. DEBUG_IRQ("rising edges\n");
  84. irq_type = 0x0;
  85. }
  86. if (type & __IRQT_FALEDGE) {
  87. DEBUG_IRQ("falling edges\n");
  88. irq_type = 0x1;
  89. }
  90. if (type & __IRQT_LOWLVL) {
  91. DEBUG_IRQ("low level\n");
  92. irq_type = 0x3;
  93. }
  94. if (type & __IRQT_HIGHLVL) {
  95. DEBUG_IRQ("high level\n");
  96. irq_type = 0x2;
  97. }
  98. if (irq % 32 < 16) {
  99. ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) |
  100. (irq_type << ((irq % 16) * 2));
  101. } else {
  102. ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) |
  103. (irq_type << ((irq % 16) * 2));
  104. }
  105. return 0;
  106. }
  107. static void
  108. imx_gpio_ack_irq(unsigned int irq)
  109. {
  110. DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
  111. ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32);
  112. }
  113. static void
  114. imx_gpio_mask_irq(unsigned int irq)
  115. {
  116. DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
  117. IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32));
  118. }
  119. static void
  120. imx_gpio_unmask_irq(unsigned int irq)
  121. {
  122. DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
  123. IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32);
  124. }
  125. static void
  126. imx_gpio_handler(unsigned int mask, unsigned int irq,
  127. struct irq_desc *desc)
  128. {
  129. desc = irq_desc + irq;
  130. while (mask) {
  131. if (mask & 1) {
  132. DEBUG_IRQ("handling irq %d\n", irq);
  133. desc_handle_irq(irq, desc);
  134. }
  135. irq++;
  136. desc++;
  137. mask >>= 1;
  138. }
  139. }
  140. static void
  141. imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
  142. {
  143. unsigned int mask, irq;
  144. mask = ISR(0);
  145. irq = IRQ_GPIOA(0);
  146. imx_gpio_handler(mask, irq, desc);
  147. }
  148. static void
  149. imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
  150. {
  151. unsigned int mask, irq;
  152. mask = ISR(1);
  153. irq = IRQ_GPIOB(0);
  154. imx_gpio_handler(mask, irq, desc);
  155. }
  156. static void
  157. imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
  158. {
  159. unsigned int mask, irq;
  160. mask = ISR(2);
  161. irq = IRQ_GPIOC(0);
  162. imx_gpio_handler(mask, irq, desc);
  163. }
  164. static void
  165. imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
  166. {
  167. unsigned int mask, irq;
  168. mask = ISR(3);
  169. irq = IRQ_GPIOD(0);
  170. imx_gpio_handler(mask, irq, desc);
  171. }
  172. static struct irq_chip imx_internal_chip = {
  173. .name = "MPU",
  174. .ack = imx_mask_irq,
  175. .mask = imx_mask_irq,
  176. .unmask = imx_unmask_irq,
  177. };
  178. static struct irq_chip imx_gpio_chip = {
  179. .name = "GPIO",
  180. .ack = imx_gpio_ack_irq,
  181. .mask = imx_gpio_mask_irq,
  182. .unmask = imx_gpio_unmask_irq,
  183. .set_type = imx_gpio_irq_type,
  184. };
  185. void __init
  186. imx_init_irq(void)
  187. {
  188. unsigned int irq;
  189. DEBUG_IRQ("Initializing imx interrupts\n");
  190. /* Mask all interrupts initially */
  191. IMR(0) = 0;
  192. IMR(1) = 0;
  193. IMR(2) = 0;
  194. IMR(3) = 0;
  195. for (irq = 0; irq < IMX_IRQS; irq++) {
  196. set_irq_chip(irq, &imx_internal_chip);
  197. set_irq_handler(irq, handle_level_irq);
  198. set_irq_flags(irq, IRQF_VALID);
  199. }
  200. for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
  201. set_irq_chip(irq, &imx_gpio_chip);
  202. set_irq_handler(irq, handle_edge_irq);
  203. set_irq_flags(irq, IRQF_VALID);
  204. }
  205. set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler);
  206. set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler);
  207. set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler);
  208. set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler);
  209. /* Disable all interrupts initially. */
  210. /* In IMX this is done in the bootloader. */
  211. }