dma.c 16 KB

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  1. /*
  2. * linux/arch/arm/mach-imx/dma.c
  3. *
  4. * imx DMA registration and IRQ dispatching
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * 2004-03-03 Sascha Hauer <sascha@saschahauer.de>
  11. * initial version heavily inspired by
  12. * linux/arch/arm/mach-pxa/dma.c
  13. *
  14. * 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
  15. * Changed to support scatter gather DMA
  16. * by taking Russell's code from RiscPC
  17. *
  18. * 2006-05-31 Pavel Pisa <pisa@cmp.felk.cvut.cz>
  19. * Corrected error handling code.
  20. *
  21. */
  22. #undef DEBUG
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/kernel.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/errno.h>
  28. #include <asm/system.h>
  29. #include <asm/irq.h>
  30. #include <asm/hardware.h>
  31. #include <asm/dma.h>
  32. #include <asm/arch/imx-dma.h>
  33. struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
  34. /*
  35. * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
  36. * @dma_ch: i.MX DMA channel number
  37. * @lastcount: number of bytes transferred during last transfer
  38. *
  39. * Functions prepares DMA controller for next sg data chunk transfer.
  40. * The @lastcount argument informs function about number of bytes transferred
  41. * during last block. Zero value can be used for @lastcount to setup DMA
  42. * for the first chunk.
  43. */
  44. static inline int imx_dma_sg_next(imx_dmach_t dma_ch, unsigned int lastcount)
  45. {
  46. struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
  47. unsigned int nextcount;
  48. unsigned int nextaddr;
  49. if (!imxdma->name) {
  50. printk(KERN_CRIT "%s: called for not allocated channel %d\n",
  51. __FUNCTION__, dma_ch);
  52. return 0;
  53. }
  54. imxdma->resbytes -= lastcount;
  55. if (!imxdma->sg) {
  56. pr_debug("imxdma%d: no sg data\n", dma_ch);
  57. return 0;
  58. }
  59. imxdma->sgbc += lastcount;
  60. if ((imxdma->sgbc >= imxdma->sg->length) || !imxdma->resbytes) {
  61. if ((imxdma->sgcount <= 1) || !imxdma->resbytes) {
  62. pr_debug("imxdma%d: sg transfer limit reached\n",
  63. dma_ch);
  64. imxdma->sgcount=0;
  65. imxdma->sg = NULL;
  66. return 0;
  67. } else {
  68. imxdma->sgcount--;
  69. imxdma->sg++;
  70. imxdma->sgbc = 0;
  71. }
  72. }
  73. nextcount = imxdma->sg->length - imxdma->sgbc;
  74. nextaddr = imxdma->sg->dma_address + imxdma->sgbc;
  75. if(imxdma->resbytes < nextcount)
  76. nextcount = imxdma->resbytes;
  77. if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
  78. DAR(dma_ch) = nextaddr;
  79. else
  80. SAR(dma_ch) = nextaddr;
  81. CNTR(dma_ch) = nextcount;
  82. pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, size 0x%08x\n",
  83. dma_ch, DAR(dma_ch), SAR(dma_ch), CNTR(dma_ch));
  84. return nextcount;
  85. }
  86. /*
  87. * imx_dma_setup_sg_base - scatter-gather DMA emulation
  88. * @dma_ch: i.MX DMA channel number
  89. * @sg: pointer to the scatter-gather list/vector
  90. * @sgcount: scatter-gather list hungs count
  91. *
  92. * Functions sets up i.MX DMA state for emulated scatter-gather transfer
  93. * and sets up channel registers to be ready for the first chunk
  94. */
  95. static int
  96. imx_dma_setup_sg_base(imx_dmach_t dma_ch,
  97. struct scatterlist *sg, unsigned int sgcount)
  98. {
  99. struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
  100. imxdma->sg = sg;
  101. imxdma->sgcount = sgcount;
  102. imxdma->sgbc = 0;
  103. return imx_dma_sg_next(dma_ch, 0);
  104. }
  105. /**
  106. * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from device transfer
  107. * @dma_ch: i.MX DMA channel number
  108. * @dma_address: the DMA/physical memory address of the linear data block
  109. * to transfer
  110. * @dma_length: length of the data block in bytes
  111. * @dev_addr: physical device port address
  112. * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
  113. * or %DMA_MODE_WRITE from memory to the device
  114. *
  115. * The function setups DMA channel source and destination addresses for transfer
  116. * specified by provided parameters. The scatter-gather emulation is disabled,
  117. * because linear data block
  118. * form the physical address range is transfered.
  119. * Return value: if incorrect parameters are provided -%EINVAL.
  120. * Zero indicates success.
  121. */
  122. int
  123. imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
  124. unsigned int dma_length, unsigned int dev_addr,
  125. dmamode_t dmamode)
  126. {
  127. struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
  128. imxdma->sg = NULL;
  129. imxdma->sgcount = 0;
  130. imxdma->dma_mode = dmamode;
  131. imxdma->resbytes = dma_length;
  132. if (!dma_address) {
  133. printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
  134. dma_ch);
  135. return -EINVAL;
  136. }
  137. if (!dma_length) {
  138. printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
  139. dma_ch);
  140. return -EINVAL;
  141. }
  142. if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
  143. pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for read\n",
  144. dma_ch, (unsigned int)dma_address, dma_length,
  145. dev_addr);
  146. SAR(dma_ch) = dev_addr;
  147. DAR(dma_ch) = (unsigned int)dma_address;
  148. } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
  149. pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for write\n",
  150. dma_ch, (unsigned int)dma_address, dma_length,
  151. dev_addr);
  152. SAR(dma_ch) = (unsigned int)dma_address;
  153. DAR(dma_ch) = dev_addr;
  154. } else {
  155. printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
  156. dma_ch);
  157. return -EINVAL;
  158. }
  159. CNTR(dma_ch) = dma_length;
  160. return 0;
  161. }
  162. /**
  163. * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
  164. * @dma_ch: i.MX DMA channel number
  165. * @sg: pointer to the scatter-gather list/vector
  166. * @sgcount: scatter-gather list hungs count
  167. * @dma_length: total length of the transfer request in bytes
  168. * @dev_addr: physical device port address
  169. * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
  170. * or %DMA_MODE_WRITE from memory to the device
  171. *
  172. * The function setups DMA channel state and registers to be ready for transfer
  173. * specified by provided parameters. The scatter-gather emulation is set up
  174. * according to the parameters.
  175. *
  176. * The full preparation of the transfer requires setup of more register
  177. * by the caller before imx_dma_enable() can be called.
  178. *
  179. * %BLR(dma_ch) holds transfer burst length in bytes, 0 means 64 bytes
  180. *
  181. * %RSSR(dma_ch) has to be set to the DMA request line source %DMA_REQ_xxx
  182. *
  183. * %CCR(dma_ch) has to specify transfer parameters, the next settings is typical
  184. * for linear or simple scatter-gather transfers if %DMA_MODE_READ is specified
  185. *
  186. * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
  187. *
  188. * The typical setup for %DMA_MODE_WRITE is specified by next options combination
  189. *
  190. * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
  191. *
  192. * Be carefull there and do not mistakenly mix source and target device
  193. * port sizes constants, they are really different:
  194. * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
  195. * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
  196. *
  197. * Return value: if incorrect parameters are provided -%EINVAL.
  198. * Zero indicates success.
  199. */
  200. int
  201. imx_dma_setup_sg(imx_dmach_t dma_ch,
  202. struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length,
  203. unsigned int dev_addr, dmamode_t dmamode)
  204. {
  205. int res;
  206. struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
  207. imxdma->sg = NULL;
  208. imxdma->sgcount = 0;
  209. imxdma->dma_mode = dmamode;
  210. imxdma->resbytes = dma_length;
  211. if (!sg || !sgcount) {
  212. printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
  213. dma_ch);
  214. return -EINVAL;
  215. }
  216. if (!sg->length) {
  217. printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
  218. dma_ch);
  219. return -EINVAL;
  220. }
  221. if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
  222. pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for read\n",
  223. dma_ch, sg, sgcount, dma_length, dev_addr);
  224. SAR(dma_ch) = dev_addr;
  225. } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
  226. pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for write\n",
  227. dma_ch, sg, sgcount, dma_length, dev_addr);
  228. DAR(dma_ch) = dev_addr;
  229. } else {
  230. printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
  231. dma_ch);
  232. return -EINVAL;
  233. }
  234. res = imx_dma_setup_sg_base(dma_ch, sg, sgcount);
  235. if (res <= 0) {
  236. printk(KERN_ERR "imxdma%d: no sg chunk ready\n", dma_ch);
  237. return -EINVAL;
  238. }
  239. return 0;
  240. }
  241. /**
  242. * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification handlers
  243. * @dma_ch: i.MX DMA channel number
  244. * @irq_handler: the pointer to the function called if the transfer
  245. * ends successfully
  246. * @err_handler: the pointer to the function called if the premature
  247. * end caused by error occurs
  248. * @data: user specified value to be passed to the handlers
  249. */
  250. int
  251. imx_dma_setup_handlers(imx_dmach_t dma_ch,
  252. void (*irq_handler) (int, void *),
  253. void (*err_handler) (int, void *, int),
  254. void *data)
  255. {
  256. struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
  257. unsigned long flags;
  258. if (!imxdma->name) {
  259. printk(KERN_CRIT "%s: called for not allocated channel %d\n",
  260. __FUNCTION__, dma_ch);
  261. return -ENODEV;
  262. }
  263. local_irq_save(flags);
  264. DISR = (1 << dma_ch);
  265. imxdma->irq_handler = irq_handler;
  266. imxdma->err_handler = err_handler;
  267. imxdma->data = data;
  268. local_irq_restore(flags);
  269. return 0;
  270. }
  271. /**
  272. * imx_dma_enable - function to start i.MX DMA channel operation
  273. * @dma_ch: i.MX DMA channel number
  274. *
  275. * The channel has to be allocated by driver through imx_dma_request()
  276. * or imx_dma_request_by_prio() function.
  277. * The transfer parameters has to be set to the channel registers through
  278. * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
  279. * and registers %BLR(dma_ch), %RSSR(dma_ch) and %CCR(dma_ch) has to
  280. * be set prior this function call by the channel user.
  281. */
  282. void imx_dma_enable(imx_dmach_t dma_ch)
  283. {
  284. struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
  285. unsigned long flags;
  286. pr_debug("imxdma%d: imx_dma_enable\n", dma_ch);
  287. if (!imxdma->name) {
  288. printk(KERN_CRIT "%s: called for not allocated channel %d\n",
  289. __FUNCTION__, dma_ch);
  290. return;
  291. }
  292. local_irq_save(flags);
  293. DISR = (1 << dma_ch);
  294. DIMR &= ~(1 << dma_ch);
  295. CCR(dma_ch) |= CCR_CEN;
  296. local_irq_restore(flags);
  297. }
  298. /**
  299. * imx_dma_disable - stop, finish i.MX DMA channel operatin
  300. * @dma_ch: i.MX DMA channel number
  301. */
  302. void imx_dma_disable(imx_dmach_t dma_ch)
  303. {
  304. unsigned long flags;
  305. pr_debug("imxdma%d: imx_dma_disable\n", dma_ch);
  306. local_irq_save(flags);
  307. DIMR |= (1 << dma_ch);
  308. CCR(dma_ch) &= ~CCR_CEN;
  309. DISR = (1 << dma_ch);
  310. local_irq_restore(flags);
  311. }
  312. /**
  313. * imx_dma_request - request/allocate specified channel number
  314. * @dma_ch: i.MX DMA channel number
  315. * @name: the driver/caller own non-%NULL identification
  316. */
  317. int imx_dma_request(imx_dmach_t dma_ch, const char *name)
  318. {
  319. struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
  320. unsigned long flags;
  321. /* basic sanity checks */
  322. if (!name)
  323. return -EINVAL;
  324. if (dma_ch >= IMX_DMA_CHANNELS) {
  325. printk(KERN_CRIT "%s: called for non-existed channel %d\n",
  326. __FUNCTION__, dma_ch);
  327. return -EINVAL;
  328. }
  329. local_irq_save(flags);
  330. if (imxdma->name) {
  331. local_irq_restore(flags);
  332. return -ENODEV;
  333. }
  334. imxdma->name = name;
  335. imxdma->irq_handler = NULL;
  336. imxdma->err_handler = NULL;
  337. imxdma->data = NULL;
  338. imxdma->sg = NULL;
  339. local_irq_restore(flags);
  340. return 0;
  341. }
  342. /**
  343. * imx_dma_free - release previously acquired channel
  344. * @dma_ch: i.MX DMA channel number
  345. */
  346. void imx_dma_free(imx_dmach_t dma_ch)
  347. {
  348. unsigned long flags;
  349. struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
  350. if (!imxdma->name) {
  351. printk(KERN_CRIT
  352. "%s: trying to free channel %d which is already freed\n",
  353. __FUNCTION__, dma_ch);
  354. return;
  355. }
  356. local_irq_save(flags);
  357. /* Disable interrupts */
  358. DIMR |= (1 << dma_ch);
  359. CCR(dma_ch) &= ~CCR_CEN;
  360. imxdma->name = NULL;
  361. local_irq_restore(flags);
  362. }
  363. /**
  364. * imx_dma_request_by_prio - find and request some of free channels best suiting requested priority
  365. * @dma_ch: i.MX DMA channel number
  366. * @name: the driver/caller own non-%NULL identification
  367. * @prio: one of the hardware distinguished priority level:
  368. * %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW
  369. *
  370. * This function tries to find free channel in the specified priority group
  371. * if the priority cannot be achieved it tries to look for free channel
  372. * in the higher and then even lower priority groups.
  373. *
  374. * Return value: If there is no free channel to allocate, -%ENODEV is returned.
  375. * Zero value indicates successful channel allocation.
  376. */
  377. int
  378. imx_dma_request_by_prio(imx_dmach_t * pdma_ch, const char *name,
  379. imx_dma_prio prio)
  380. {
  381. int i;
  382. int best;
  383. switch (prio) {
  384. case (DMA_PRIO_HIGH):
  385. best = 8;
  386. break;
  387. case (DMA_PRIO_MEDIUM):
  388. best = 4;
  389. break;
  390. case (DMA_PRIO_LOW):
  391. default:
  392. best = 0;
  393. break;
  394. }
  395. for (i = best; i < IMX_DMA_CHANNELS; i++) {
  396. if (!imx_dma_request(i, name)) {
  397. *pdma_ch = i;
  398. return 0;
  399. }
  400. }
  401. for (i = best - 1; i >= 0; i--) {
  402. if (!imx_dma_request(i, name)) {
  403. *pdma_ch = i;
  404. return 0;
  405. }
  406. }
  407. printk(KERN_ERR "%s: no free DMA channel found\n", __FUNCTION__);
  408. return -ENODEV;
  409. }
  410. static irqreturn_t dma_err_handler(int irq, void *dev_id)
  411. {
  412. int i, disr = DISR;
  413. struct imx_dma_channel *channel;
  414. unsigned int err_mask = DBTOSR | DRTOSR | DSESR | DBOSR;
  415. int errcode;
  416. DISR = disr & err_mask;
  417. for (i = 0; i < IMX_DMA_CHANNELS; i++) {
  418. if(!(err_mask & (1 << i)))
  419. continue;
  420. channel = &imx_dma_channels[i];
  421. errcode = 0;
  422. if (DBTOSR & (1 << i)) {
  423. DBTOSR = (1 << i);
  424. errcode |= IMX_DMA_ERR_BURST;
  425. }
  426. if (DRTOSR & (1 << i)) {
  427. DRTOSR = (1 << i);
  428. errcode |= IMX_DMA_ERR_REQUEST;
  429. }
  430. if (DSESR & (1 << i)) {
  431. DSESR = (1 << i);
  432. errcode |= IMX_DMA_ERR_TRANSFER;
  433. }
  434. if (DBOSR & (1 << i)) {
  435. DBOSR = (1 << i);
  436. errcode |= IMX_DMA_ERR_BUFFER;
  437. }
  438. /*
  439. * The cleaning of @sg field would be questionable
  440. * there, because its value can help to compute
  441. * remaining/transfered bytes count in the handler
  442. */
  443. /*imx_dma_channels[i].sg = NULL;*/
  444. if (channel->name && channel->err_handler) {
  445. channel->err_handler(i, channel->data, errcode);
  446. continue;
  447. }
  448. imx_dma_channels[i].sg = NULL;
  449. printk(KERN_WARNING
  450. "DMA timeout on channel %d (%s) -%s%s%s%s\n",
  451. i, channel->name,
  452. errcode&IMX_DMA_ERR_BURST? " burst":"",
  453. errcode&IMX_DMA_ERR_REQUEST? " request":"",
  454. errcode&IMX_DMA_ERR_TRANSFER? " transfer":"",
  455. errcode&IMX_DMA_ERR_BUFFER? " buffer":"");
  456. }
  457. return IRQ_HANDLED;
  458. }
  459. static irqreturn_t dma_irq_handler(int irq, void *dev_id)
  460. {
  461. int i, disr = DISR;
  462. pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
  463. disr);
  464. DISR = disr;
  465. for (i = 0; i < IMX_DMA_CHANNELS; i++) {
  466. if (disr & (1 << i)) {
  467. struct imx_dma_channel *channel = &imx_dma_channels[i];
  468. if (channel->name) {
  469. if (imx_dma_sg_next(i, CNTR(i))) {
  470. CCR(i) &= ~CCR_CEN;
  471. mb();
  472. CCR(i) |= CCR_CEN;
  473. } else {
  474. if (channel->irq_handler)
  475. channel->irq_handler(i,
  476. channel->data);
  477. }
  478. } else {
  479. /*
  480. * IRQ for an unregistered DMA channel:
  481. * let's clear the interrupts and disable it.
  482. */
  483. printk(KERN_WARNING
  484. "spurious IRQ for DMA channel %d\n", i);
  485. }
  486. }
  487. }
  488. return IRQ_HANDLED;
  489. }
  490. static int __init imx_dma_init(void)
  491. {
  492. int ret;
  493. int i;
  494. /* reset DMA module */
  495. DCR = DCR_DRST;
  496. ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
  497. if (ret) {
  498. printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n");
  499. return ret;
  500. }
  501. ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL);
  502. if (ret) {
  503. printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n");
  504. free_irq(DMA_INT, NULL);
  505. }
  506. /* enable DMA module */
  507. DCR = DCR_DEN;
  508. /* clear all interrupts */
  509. DISR = (1 << IMX_DMA_CHANNELS) - 1;
  510. /* enable interrupts */
  511. DIMR = (1 << IMX_DMA_CHANNELS) - 1;
  512. for (i = 0; i < IMX_DMA_CHANNELS; i++) {
  513. imx_dma_channels[i].sg = NULL;
  514. imx_dma_channels[i].dma_num = i;
  515. }
  516. return ret;
  517. }
  518. arch_initcall(imx_dma_init);
  519. EXPORT_SYMBOL(imx_dma_setup_single);
  520. EXPORT_SYMBOL(imx_dma_setup_sg);
  521. EXPORT_SYMBOL(imx_dma_setup_handlers);
  522. EXPORT_SYMBOL(imx_dma_enable);
  523. EXPORT_SYMBOL(imx_dma_disable);
  524. EXPORT_SYMBOL(imx_dma_request);
  525. EXPORT_SYMBOL(imx_dma_free);
  526. EXPORT_SYMBOL(imx_dma_request_by_prio);
  527. EXPORT_SYMBOL(imx_dma_channels);