cpu-h7202.c 5.2 KB

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  1. /*
  2. * linux/arch/arm/mach-h720x/cpu-h7202.c
  3. *
  4. * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
  5. * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
  6. * 2004 Sascha Hauer <s.hauer@pengutronix.de>
  7. *
  8. * processor specific stuff for the Hynix h7202
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. */
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/module.h>
  18. #include <asm/types.h>
  19. #include <asm/hardware.h>
  20. #include <asm/irq.h>
  21. #include <asm/arch/irqs.h>
  22. #include <asm/mach/irq.h>
  23. #include <asm/mach/time.h>
  24. #include <linux/device.h>
  25. #include <linux/serial_8250.h>
  26. #include "common.h"
  27. static struct resource h7202ps2_resources[] = {
  28. [0] = {
  29. .start = 0x8002c000,
  30. .end = 0x8002c040,
  31. .flags = IORESOURCE_MEM,
  32. },
  33. [1] = {
  34. .start = IRQ_PS2,
  35. .end = IRQ_PS2,
  36. .flags = IORESOURCE_IRQ,
  37. },
  38. };
  39. static struct platform_device h7202ps2_device = {
  40. .name = "h7202ps2",
  41. .id = -1,
  42. .num_resources = ARRAY_SIZE(h7202ps2_resources),
  43. .resource = h7202ps2_resources,
  44. };
  45. static struct plat_serial8250_port serial_platform_data[] = {
  46. {
  47. .membase = (void*)SERIAL0_VIRT,
  48. .mapbase = SERIAL0_BASE,
  49. .irq = IRQ_UART0,
  50. .uartclk = 2*1843200,
  51. .regshift = 2,
  52. .iotype = UPIO_MEM,
  53. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  54. },
  55. {
  56. .membase = (void*)SERIAL1_VIRT,
  57. .mapbase = SERIAL1_BASE,
  58. .irq = IRQ_UART1,
  59. .uartclk = 2*1843200,
  60. .regshift = 2,
  61. .iotype = UPIO_MEM,
  62. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  63. },
  64. #ifdef CONFIG_H7202_SERIAL23
  65. {
  66. .membase = (void*)SERIAL2_VIRT,
  67. .mapbase = SERIAL2_BASE,
  68. .irq = IRQ_UART2,
  69. .uartclk = 2*1843200,
  70. .regshift = 2,
  71. .iotype = UPIO_MEM,
  72. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  73. },
  74. {
  75. .membase = (void*)SERIAL3_VIRT,
  76. .mapbase = SERIAL3_BASE,
  77. .irq = IRQ_UART3,
  78. .uartclk = 2*1843200,
  79. .regshift = 2,
  80. .iotype = UPIO_MEM,
  81. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  82. },
  83. #endif
  84. { },
  85. };
  86. static struct platform_device serial_device = {
  87. .name = "serial8250",
  88. .id = PLAT8250_DEV_PLATFORM,
  89. .dev = {
  90. .platform_data = serial_platform_data,
  91. },
  92. };
  93. static struct platform_device *devices[] __initdata = {
  94. &h7202ps2_device,
  95. &serial_device,
  96. };
  97. /* Although we have two interrupt lines for the timers, we only have one
  98. * status register which clears all pending timer interrupts on reading. So
  99. * we have to handle all timer interrupts in one place.
  100. */
  101. static void
  102. h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
  103. {
  104. unsigned int mask, irq;
  105. mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
  106. if ( mask & TSTAT_T0INT ) {
  107. write_seqlock(&xtime_lock);
  108. timer_tick();
  109. write_sequnlock(&xtime_lock);
  110. if( mask == TSTAT_T0INT )
  111. return;
  112. }
  113. mask >>= 1;
  114. irq = IRQ_TIMER1;
  115. desc = irq_desc + irq;
  116. while (mask) {
  117. if (mask & 1)
  118. desc_handle_irq(irq, desc);
  119. irq++;
  120. desc++;
  121. mask >>= 1;
  122. }
  123. }
  124. /*
  125. * Timer interrupt handler
  126. */
  127. static irqreturn_t
  128. h7202_timer_interrupt(int irq, void *dev_id)
  129. {
  130. h7202_timerx_demux_handler(0, NULL);
  131. return IRQ_HANDLED;
  132. }
  133. /*
  134. * mask multiplexed timer irq's
  135. */
  136. static void inline mask_timerx_irq (u32 irq)
  137. {
  138. unsigned int bit;
  139. bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
  140. CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
  141. }
  142. /*
  143. * unmask multiplexed timer irq's
  144. */
  145. static void inline unmask_timerx_irq (u32 irq)
  146. {
  147. unsigned int bit;
  148. bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
  149. CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
  150. }
  151. static struct irq_chip h7202_timerx_chip = {
  152. .ack = mask_timerx_irq,
  153. .mask = mask_timerx_irq,
  154. .unmask = unmask_timerx_irq,
  155. };
  156. static struct irqaction h7202_timer_irq = {
  157. .name = "h7202 Timer Tick",
  158. .flags = IRQF_DISABLED | IRQF_TIMER,
  159. .handler = h7202_timer_interrupt,
  160. };
  161. /*
  162. * Setup TIMER0 as system timer
  163. */
  164. void __init h7202_init_time(void)
  165. {
  166. CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
  167. CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
  168. CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
  169. CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
  170. setup_irq(IRQ_TIMER0, &h7202_timer_irq);
  171. }
  172. struct sys_timer h7202_timer = {
  173. .init = h7202_init_time,
  174. .offset = h720x_gettimeoffset,
  175. };
  176. void __init h7202_init_irq (void)
  177. {
  178. int irq;
  179. CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0;
  180. for (irq = IRQ_TIMER1;
  181. irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
  182. mask_timerx_irq(irq);
  183. set_irq_chip(irq, &h7202_timerx_chip);
  184. set_irq_handler(irq, handle_edge_irq);
  185. set_irq_flags(irq, IRQF_VALID );
  186. }
  187. set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
  188. h720x_init_irq();
  189. }
  190. void __init init_hw_h7202(void)
  191. {
  192. /* Enable clocks */
  193. CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;
  194. CPU_REG (SERIAL0_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
  195. CPU_REG (SERIAL1_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
  196. #ifdef CONFIG_H7202_SERIAL23
  197. CPU_REG (SERIAL2_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
  198. CPU_REG (SERIAL3_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
  199. CPU_IO (GPIO_AMULSEL) = AMULSEL_USIN2 | AMULSEL_USOUT2 |
  200. AMULSEL_USIN3 | AMULSEL_USOUT3;
  201. #endif
  202. (void) platform_add_devices(devices, ARRAY_SIZE(devices));
  203. }