common.c 5.7 KB

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  1. /*
  2. * linux/arch/arm/mach-h720x/common.c
  3. *
  4. * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
  5. * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
  6. * 2004 Sascha Hauer <s.hauer@pengutronix.de>
  7. *
  8. * common stuff for Hynix h720x processors
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. */
  15. #include <linux/sched.h>
  16. #include <linux/slab.h>
  17. #include <linux/mman.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <asm/page.h>
  21. #include <asm/pgtable.h>
  22. #include <asm/dma.h>
  23. #include <asm/io.h>
  24. #include <asm/hardware.h>
  25. #include <asm/irq.h>
  26. #include <asm/mach/irq.h>
  27. #include <asm/mach/map.h>
  28. #include <asm/arch/irqs.h>
  29. #include <asm/mach/dma.h>
  30. #if 0
  31. #define IRQDBG(args...) printk(args)
  32. #else
  33. #define IRQDBG(args...) do {} while(0)
  34. #endif
  35. void __init arch_dma_init(dma_t *dma)
  36. {
  37. }
  38. /*
  39. * Return usecs since last timer reload
  40. * (timercount * (usecs perjiffie)) / (ticks per jiffie)
  41. */
  42. unsigned long h720x_gettimeoffset(void)
  43. {
  44. return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH;
  45. }
  46. /*
  47. * mask Global irq's
  48. */
  49. static void mask_global_irq (unsigned int irq )
  50. {
  51. CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq);
  52. }
  53. /*
  54. * unmask Global irq's
  55. */
  56. static void unmask_global_irq (unsigned int irq )
  57. {
  58. CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq);
  59. }
  60. /*
  61. * ack GPIO irq's
  62. * Ack only for edge triggered int's valid
  63. */
  64. static void inline ack_gpio_irq(u32 irq)
  65. {
  66. u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
  67. u32 bit = IRQ_TO_BIT(irq);
  68. if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
  69. CPU_REG (reg_base, GPIO_CLR) = bit;
  70. }
  71. /*
  72. * mask GPIO irq's
  73. */
  74. static void inline mask_gpio_irq(u32 irq)
  75. {
  76. u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
  77. u32 bit = IRQ_TO_BIT(irq);
  78. CPU_REG (reg_base, GPIO_MASK) &= ~bit;
  79. }
  80. /*
  81. * unmask GPIO irq's
  82. */
  83. static void inline unmask_gpio_irq(u32 irq)
  84. {
  85. u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
  86. u32 bit = IRQ_TO_BIT(irq);
  87. CPU_REG (reg_base, GPIO_MASK) |= bit;
  88. }
  89. static void
  90. h720x_gpio_handler(unsigned int mask, unsigned int irq,
  91. struct irq_desc *desc)
  92. {
  93. IRQDBG("%s irq: %d\n",__FUNCTION__,irq);
  94. desc = irq_desc + irq;
  95. while (mask) {
  96. if (mask & 1) {
  97. IRQDBG("handling irq %d\n", irq);
  98. desc_handle_irq(irq, desc);
  99. }
  100. irq++;
  101. desc++;
  102. mask >>= 1;
  103. }
  104. }
  105. static void
  106. h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
  107. {
  108. unsigned int mask, irq;
  109. mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
  110. irq = IRQ_CHAINED_GPIOA(0);
  111. IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
  112. h720x_gpio_handler(mask, irq, desc);
  113. }
  114. static void
  115. h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
  116. {
  117. unsigned int mask, irq;
  118. mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
  119. irq = IRQ_CHAINED_GPIOB(0);
  120. IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
  121. h720x_gpio_handler(mask, irq, desc);
  122. }
  123. static void
  124. h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
  125. {
  126. unsigned int mask, irq;
  127. mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
  128. irq = IRQ_CHAINED_GPIOC(0);
  129. IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
  130. h720x_gpio_handler(mask, irq, desc);
  131. }
  132. static void
  133. h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
  134. {
  135. unsigned int mask, irq;
  136. mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
  137. irq = IRQ_CHAINED_GPIOD(0);
  138. IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
  139. h720x_gpio_handler(mask, irq, desc);
  140. }
  141. #ifdef CONFIG_CPU_H7202
  142. static void
  143. h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
  144. {
  145. unsigned int mask, irq;
  146. mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
  147. irq = IRQ_CHAINED_GPIOE(0);
  148. IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
  149. h720x_gpio_handler(mask, irq, desc);
  150. }
  151. #endif
  152. static struct irq_chip h720x_global_chip = {
  153. .ack = mask_global_irq,
  154. .mask = mask_global_irq,
  155. .unmask = unmask_global_irq,
  156. };
  157. static struct irq_chip h720x_gpio_chip = {
  158. .ack = ack_gpio_irq,
  159. .mask = mask_gpio_irq,
  160. .unmask = unmask_gpio_irq,
  161. };
  162. /*
  163. * Initialize IRQ's, mask all, enable multiplexed irq's
  164. */
  165. void __init h720x_init_irq (void)
  166. {
  167. int irq;
  168. /* Mask global irq's */
  169. CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
  170. /* Mask all multiplexed irq's */
  171. CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
  172. CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
  173. CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
  174. CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
  175. /* Initialize global IRQ's, fast path */
  176. for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
  177. set_irq_chip(irq, &h720x_global_chip);
  178. set_irq_handler(irq, handle_level_irq);
  179. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  180. }
  181. /* Initialize multiplexed IRQ's, slow path */
  182. for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
  183. set_irq_chip(irq, &h720x_gpio_chip);
  184. set_irq_handler(irq, handle_edge_irq);
  185. set_irq_flags(irq, IRQF_VALID );
  186. }
  187. set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
  188. set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
  189. set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
  190. set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
  191. #ifdef CONFIG_CPU_H7202
  192. for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
  193. set_irq_chip(irq, &h720x_gpio_chip);
  194. set_irq_handler(irq, handle_edge_irq);
  195. set_irq_flags(irq, IRQF_VALID );
  196. }
  197. set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
  198. #endif
  199. /* Enable multiplexed irq's */
  200. CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
  201. }
  202. static struct map_desc h720x_io_desc[] __initdata = {
  203. {
  204. .virtual = IO_VIRT,
  205. .pfn = __phys_to_pfn(IO_PHYS),
  206. .length = IO_SIZE,
  207. .type = MT_DEVICE
  208. },
  209. };
  210. /* Initialize io tables */
  211. void __init h720x_map_io(void)
  212. {
  213. iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
  214. }