dc21285.c 9.0 KB

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  1. /*
  2. * linux/arch/arm/kernel/dec21285.c: PCI functions for DC21285
  3. *
  4. * Copyright (C) 1998-2001 Russell King
  5. * Copyright (C) 1998-2000 Phil Blundell
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/pci.h>
  13. #include <linux/ptrace.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/mm.h>
  16. #include <linux/slab.h>
  17. #include <linux/init.h>
  18. #include <linux/ioport.h>
  19. #include <linux/irq.h>
  20. #include <asm/io.h>
  21. #include <asm/irq.h>
  22. #include <asm/system.h>
  23. #include <asm/mach/pci.h>
  24. #include <asm/hardware/dec21285.h>
  25. #define MAX_SLOTS 21
  26. #define PCICMD_ABORT ((PCI_STATUS_REC_MASTER_ABORT| \
  27. PCI_STATUS_REC_TARGET_ABORT)<<16)
  28. #define PCICMD_ERROR_BITS ((PCI_STATUS_DETECTED_PARITY | \
  29. PCI_STATUS_REC_MASTER_ABORT | \
  30. PCI_STATUS_REC_TARGET_ABORT | \
  31. PCI_STATUS_PARITY) << 16)
  32. extern int setup_arm_irq(int, struct irqaction *);
  33. extern void pcibios_report_status(u_int status_mask, int warn);
  34. static unsigned long
  35. dc21285_base_address(struct pci_bus *bus, unsigned int devfn)
  36. {
  37. unsigned long addr = 0;
  38. if (bus->number == 0) {
  39. if (PCI_SLOT(devfn) == 0)
  40. /*
  41. * For devfn 0, point at the 21285
  42. */
  43. addr = ARMCSR_BASE;
  44. else {
  45. devfn -= 1 << 3;
  46. if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
  47. addr = PCICFG0_BASE | 0xc00000 | (devfn << 8);
  48. }
  49. } else
  50. addr = PCICFG1_BASE | (bus->number << 16) | (devfn << 8);
  51. return addr;
  52. }
  53. static int
  54. dc21285_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  55. int size, u32 *value)
  56. {
  57. unsigned long addr = dc21285_base_address(bus, devfn);
  58. u32 v = 0xffffffff;
  59. if (addr)
  60. switch (size) {
  61. case 1:
  62. asm("ldrb %0, [%1, %2]"
  63. : "=r" (v) : "r" (addr), "r" (where) : "cc");
  64. break;
  65. case 2:
  66. asm("ldrh %0, [%1, %2]"
  67. : "=r" (v) : "r" (addr), "r" (where) : "cc");
  68. break;
  69. case 4:
  70. asm("ldr %0, [%1, %2]"
  71. : "=r" (v) : "r" (addr), "r" (where) : "cc");
  72. break;
  73. }
  74. *value = v;
  75. v = *CSR_PCICMD;
  76. if (v & PCICMD_ABORT) {
  77. *CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
  78. return -1;
  79. }
  80. return PCIBIOS_SUCCESSFUL;
  81. }
  82. static int
  83. dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where,
  84. int size, u32 value)
  85. {
  86. unsigned long addr = dc21285_base_address(bus, devfn);
  87. u32 v;
  88. if (addr)
  89. switch (size) {
  90. case 1:
  91. asm("strb %0, [%1, %2]"
  92. : : "r" (value), "r" (addr), "r" (where)
  93. : "cc");
  94. break;
  95. case 2:
  96. asm("strh %0, [%1, %2]"
  97. : : "r" (value), "r" (addr), "r" (where)
  98. : "cc");
  99. break;
  100. case 4:
  101. asm("str %0, [%1, %2]"
  102. : : "r" (value), "r" (addr), "r" (where)
  103. : "cc");
  104. break;
  105. }
  106. v = *CSR_PCICMD;
  107. if (v & PCICMD_ABORT) {
  108. *CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
  109. return -1;
  110. }
  111. return PCIBIOS_SUCCESSFUL;
  112. }
  113. static struct pci_ops dc21285_ops = {
  114. .read = dc21285_read_config,
  115. .write = dc21285_write_config,
  116. };
  117. static struct timer_list serr_timer;
  118. static struct timer_list perr_timer;
  119. static void dc21285_enable_error(unsigned long __data)
  120. {
  121. switch (__data) {
  122. case IRQ_PCI_SERR:
  123. del_timer(&serr_timer);
  124. break;
  125. case IRQ_PCI_PERR:
  126. del_timer(&perr_timer);
  127. break;
  128. }
  129. enable_irq(__data);
  130. }
  131. /*
  132. * Warn on PCI errors.
  133. */
  134. static irqreturn_t dc21285_abort_irq(int irq, void *dev_id)
  135. {
  136. unsigned int cmd;
  137. unsigned int status;
  138. cmd = *CSR_PCICMD;
  139. status = cmd >> 16;
  140. cmd = cmd & 0xffff;
  141. if (status & PCI_STATUS_REC_MASTER_ABORT) {
  142. printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n",
  143. instruction_pointer(get_irq_regs()));
  144. cmd |= PCI_STATUS_REC_MASTER_ABORT << 16;
  145. }
  146. if (status & PCI_STATUS_REC_TARGET_ABORT) {
  147. printk(KERN_DEBUG "PCI: target abort: ");
  148. pcibios_report_status(PCI_STATUS_REC_MASTER_ABORT |
  149. PCI_STATUS_SIG_TARGET_ABORT |
  150. PCI_STATUS_REC_TARGET_ABORT, 1);
  151. printk("\n");
  152. cmd |= PCI_STATUS_REC_TARGET_ABORT << 16;
  153. }
  154. *CSR_PCICMD = cmd;
  155. return IRQ_HANDLED;
  156. }
  157. static irqreturn_t dc21285_serr_irq(int irq, void *dev_id)
  158. {
  159. struct timer_list *timer = dev_id;
  160. unsigned int cntl;
  161. printk(KERN_DEBUG "PCI: system error received: ");
  162. pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1);
  163. printk("\n");
  164. cntl = *CSR_SA110_CNTL & 0xffffdf07;
  165. *CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR;
  166. /*
  167. * back off this interrupt
  168. */
  169. disable_irq(irq);
  170. timer->expires = jiffies + HZ;
  171. add_timer(timer);
  172. return IRQ_HANDLED;
  173. }
  174. static irqreturn_t dc21285_discard_irq(int irq, void *dev_id)
  175. {
  176. printk(KERN_DEBUG "PCI: discard timer expired\n");
  177. *CSR_SA110_CNTL &= 0xffffde07;
  178. return IRQ_HANDLED;
  179. }
  180. static irqreturn_t dc21285_dparity_irq(int irq, void *dev_id)
  181. {
  182. unsigned int cmd;
  183. printk(KERN_DEBUG "PCI: data parity error detected: ");
  184. pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1);
  185. printk("\n");
  186. cmd = *CSR_PCICMD & 0xffff;
  187. *CSR_PCICMD = cmd | 1 << 24;
  188. return IRQ_HANDLED;
  189. }
  190. static irqreturn_t dc21285_parity_irq(int irq, void *dev_id)
  191. {
  192. struct timer_list *timer = dev_id;
  193. unsigned int cmd;
  194. printk(KERN_DEBUG "PCI: parity error detected: ");
  195. pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1);
  196. printk("\n");
  197. cmd = *CSR_PCICMD & 0xffff;
  198. *CSR_PCICMD = cmd | 1 << 31;
  199. /*
  200. * back off this interrupt
  201. */
  202. disable_irq(irq);
  203. timer->expires = jiffies + HZ;
  204. add_timer(timer);
  205. return IRQ_HANDLED;
  206. }
  207. int __init dc21285_setup(int nr, struct pci_sys_data *sys)
  208. {
  209. struct resource *res;
  210. if (nr || !footbridge_cfn_mode())
  211. return 0;
  212. res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
  213. if (!res) {
  214. printk("out of memory for root bus resources");
  215. return 0;
  216. }
  217. res[0].flags = IORESOURCE_MEM;
  218. res[0].name = "Footbridge non-prefetch";
  219. res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
  220. res[1].name = "Footbridge prefetch";
  221. allocate_resource(&iomem_resource, &res[1], 0x20000000,
  222. 0xa0000000, 0xffffffff, 0x20000000, NULL, NULL);
  223. allocate_resource(&iomem_resource, &res[0], 0x40000000,
  224. 0x80000000, 0xffffffff, 0x40000000, NULL, NULL);
  225. sys->resource[0] = &ioport_resource;
  226. sys->resource[1] = &res[0];
  227. sys->resource[2] = &res[1];
  228. sys->mem_offset = DC21285_PCI_MEM;
  229. return 1;
  230. }
  231. struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys)
  232. {
  233. return pci_scan_bus(0, &dc21285_ops, sys);
  234. }
  235. void __init dc21285_preinit(void)
  236. {
  237. unsigned int mem_size, mem_mask;
  238. int cfn_mode;
  239. mem_size = (unsigned int)high_memory - PAGE_OFFSET;
  240. for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
  241. if (mem_mask >= mem_size)
  242. break;
  243. /*
  244. * These registers need to be set up whether we're the
  245. * central function or not.
  246. */
  247. *CSR_SDRAMBASEMASK = (mem_mask - 1) & 0x0ffc0000;
  248. *CSR_SDRAMBASEOFFSET = 0;
  249. *CSR_ROMBASEMASK = 0x80000000;
  250. *CSR_CSRBASEMASK = 0;
  251. *CSR_CSRBASEOFFSET = 0;
  252. *CSR_PCIADDR_EXTN = 0;
  253. cfn_mode = __footbridge_cfn_mode();
  254. printk(KERN_INFO "PCI: DC21285 footbridge, revision %02lX, in "
  255. "%s mode\n", *CSR_CLASSREV & 0xff, cfn_mode ?
  256. "central function" : "addin");
  257. if (footbridge_cfn_mode()) {
  258. /*
  259. * Clear any existing errors - we aren't
  260. * interested in historical data...
  261. */
  262. *CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) |
  263. SA110_CNTL_RXSERR;
  264. *CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS;
  265. }
  266. init_timer(&serr_timer);
  267. init_timer(&perr_timer);
  268. serr_timer.data = IRQ_PCI_SERR;
  269. serr_timer.function = dc21285_enable_error;
  270. perr_timer.data = IRQ_PCI_PERR;
  271. perr_timer.function = dc21285_enable_error;
  272. /*
  273. * We don't care if these fail.
  274. */
  275. request_irq(IRQ_PCI_SERR, dc21285_serr_irq, IRQF_DISABLED,
  276. "PCI system error", &serr_timer);
  277. request_irq(IRQ_PCI_PERR, dc21285_parity_irq, IRQF_DISABLED,
  278. "PCI parity error", &perr_timer);
  279. request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, IRQF_DISABLED,
  280. "PCI abort", NULL);
  281. request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, IRQF_DISABLED,
  282. "Discard timer", NULL);
  283. request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, IRQF_DISABLED,
  284. "PCI data parity", NULL);
  285. if (cfn_mode) {
  286. static struct resource csrio;
  287. csrio.flags = IORESOURCE_IO;
  288. csrio.name = "Footbridge";
  289. allocate_resource(&ioport_resource, &csrio, 128,
  290. 0xff00, 0xffff, 128, NULL, NULL);
  291. /*
  292. * Map our SDRAM at a known address in PCI space, just in case
  293. * the firmware had other ideas. Using a nonzero base is
  294. * necessary, since some VGA cards forcefully use PCI addresses
  295. * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
  296. */
  297. *CSR_PCICSRBASE = 0xf4000000;
  298. *CSR_PCICSRIOBASE = csrio.start;
  299. *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET);
  300. *CSR_PCIROMBASE = 0;
  301. *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  302. PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS;
  303. } else if (footbridge_cfn_mode() != 0) {
  304. /*
  305. * If we are not compiled to accept "add-in" mode, then
  306. * we are using a constant virt_to_bus translation which
  307. * can not hope to cater for the way the host BIOS has
  308. * set up the machine.
  309. */
  310. panic("PCI: this kernel is compiled for central "
  311. "function mode only");
  312. }
  313. }
  314. void __init dc21285_postinit(void)
  315. {
  316. register_isa_ports(DC21285_PCI_MEM, DC21285_PCI_IO, 0);
  317. }