core.c 8.2 KB

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  1. /*
  2. * linux/arch/arm/mach-clps7500/core.c
  3. *
  4. * Copyright (C) 1998 Russell King
  5. * Copyright (C) 1999 Nexus Electronics Ltd
  6. *
  7. * Extra MM routines for CL7500 architecture
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/types.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/irq.h>
  13. #include <linux/list.h>
  14. #include <linux/sched.h>
  15. #include <linux/init.h>
  16. #include <linux/device.h>
  17. #include <linux/serial_8250.h>
  18. #include <asm/mach/arch.h>
  19. #include <asm/mach/map.h>
  20. #include <asm/mach/irq.h>
  21. #include <asm/mach/time.h>
  22. #include <asm/hardware.h>
  23. #include <asm/hardware/iomd.h>
  24. #include <asm/io.h>
  25. #include <asm/irq.h>
  26. #include <asm/mach-types.h>
  27. unsigned int vram_size;
  28. static void cl7500_ack_irq_a(unsigned int irq)
  29. {
  30. unsigned int val, mask;
  31. mask = 1 << irq;
  32. val = iomd_readb(IOMD_IRQMASKA);
  33. iomd_writeb(val & ~mask, IOMD_IRQMASKA);
  34. iomd_writeb(mask, IOMD_IRQCLRA);
  35. }
  36. static void cl7500_mask_irq_a(unsigned int irq)
  37. {
  38. unsigned int val, mask;
  39. mask = 1 << irq;
  40. val = iomd_readb(IOMD_IRQMASKA);
  41. iomd_writeb(val & ~mask, IOMD_IRQMASKA);
  42. }
  43. static void cl7500_unmask_irq_a(unsigned int irq)
  44. {
  45. unsigned int val, mask;
  46. mask = 1 << irq;
  47. val = iomd_readb(IOMD_IRQMASKA);
  48. iomd_writeb(val | mask, IOMD_IRQMASKA);
  49. }
  50. static struct irq_chip clps7500_a_chip = {
  51. .ack = cl7500_ack_irq_a,
  52. .mask = cl7500_mask_irq_a,
  53. .unmask = cl7500_unmask_irq_a,
  54. };
  55. static void cl7500_mask_irq_b(unsigned int irq)
  56. {
  57. unsigned int val, mask;
  58. mask = 1 << (irq & 7);
  59. val = iomd_readb(IOMD_IRQMASKB);
  60. iomd_writeb(val & ~mask, IOMD_IRQMASKB);
  61. }
  62. static void cl7500_unmask_irq_b(unsigned int irq)
  63. {
  64. unsigned int val, mask;
  65. mask = 1 << (irq & 7);
  66. val = iomd_readb(IOMD_IRQMASKB);
  67. iomd_writeb(val | mask, IOMD_IRQMASKB);
  68. }
  69. static struct irq_chip clps7500_b_chip = {
  70. .ack = cl7500_mask_irq_b,
  71. .mask = cl7500_mask_irq_b,
  72. .unmask = cl7500_unmask_irq_b,
  73. };
  74. static void cl7500_mask_irq_c(unsigned int irq)
  75. {
  76. unsigned int val, mask;
  77. mask = 1 << (irq & 7);
  78. val = iomd_readb(IOMD_IRQMASKC);
  79. iomd_writeb(val & ~mask, IOMD_IRQMASKC);
  80. }
  81. static void cl7500_unmask_irq_c(unsigned int irq)
  82. {
  83. unsigned int val, mask;
  84. mask = 1 << (irq & 7);
  85. val = iomd_readb(IOMD_IRQMASKC);
  86. iomd_writeb(val | mask, IOMD_IRQMASKC);
  87. }
  88. static struct irq_chip clps7500_c_chip = {
  89. .ack = cl7500_mask_irq_c,
  90. .mask = cl7500_mask_irq_c,
  91. .unmask = cl7500_unmask_irq_c,
  92. };
  93. static void cl7500_mask_irq_d(unsigned int irq)
  94. {
  95. unsigned int val, mask;
  96. mask = 1 << (irq & 7);
  97. val = iomd_readb(IOMD_IRQMASKD);
  98. iomd_writeb(val & ~mask, IOMD_IRQMASKD);
  99. }
  100. static void cl7500_unmask_irq_d(unsigned int irq)
  101. {
  102. unsigned int val, mask;
  103. mask = 1 << (irq & 7);
  104. val = iomd_readb(IOMD_IRQMASKD);
  105. iomd_writeb(val | mask, IOMD_IRQMASKD);
  106. }
  107. static struct irq_chip clps7500_d_chip = {
  108. .ack = cl7500_mask_irq_d,
  109. .mask = cl7500_mask_irq_d,
  110. .unmask = cl7500_unmask_irq_d,
  111. };
  112. static void cl7500_mask_irq_dma(unsigned int irq)
  113. {
  114. unsigned int val, mask;
  115. mask = 1 << (irq & 7);
  116. val = iomd_readb(IOMD_DMAMASK);
  117. iomd_writeb(val & ~mask, IOMD_DMAMASK);
  118. }
  119. static void cl7500_unmask_irq_dma(unsigned int irq)
  120. {
  121. unsigned int val, mask;
  122. mask = 1 << (irq & 7);
  123. val = iomd_readb(IOMD_DMAMASK);
  124. iomd_writeb(val | mask, IOMD_DMAMASK);
  125. }
  126. static struct irq_chip clps7500_dma_chip = {
  127. .ack = cl7500_mask_irq_dma,
  128. .mask = cl7500_mask_irq_dma,
  129. .unmask = cl7500_unmask_irq_dma,
  130. };
  131. static void cl7500_mask_irq_fiq(unsigned int irq)
  132. {
  133. unsigned int val, mask;
  134. mask = 1 << (irq & 7);
  135. val = iomd_readb(IOMD_FIQMASK);
  136. iomd_writeb(val & ~mask, IOMD_FIQMASK);
  137. }
  138. static void cl7500_unmask_irq_fiq(unsigned int irq)
  139. {
  140. unsigned int val, mask;
  141. mask = 1 << (irq & 7);
  142. val = iomd_readb(IOMD_FIQMASK);
  143. iomd_writeb(val | mask, IOMD_FIQMASK);
  144. }
  145. static struct irq_chip clps7500_fiq_chip = {
  146. .ack = cl7500_mask_irq_fiq,
  147. .mask = cl7500_mask_irq_fiq,
  148. .unmask = cl7500_unmask_irq_fiq,
  149. };
  150. static void cl7500_no_action(unsigned int irq)
  151. {
  152. }
  153. static struct irq_chip clps7500_no_chip = {
  154. .ack = cl7500_no_action,
  155. .mask = cl7500_no_action,
  156. .unmask = cl7500_no_action,
  157. };
  158. static struct irqaction irq_isa = { no_action, 0, CPU_MASK_NONE, "isa", NULL, NULL };
  159. static void __init clps7500_init_irq(void)
  160. {
  161. unsigned int irq, flags;
  162. iomd_writeb(0, IOMD_IRQMASKA);
  163. iomd_writeb(0, IOMD_IRQMASKB);
  164. iomd_writeb(0, IOMD_FIQMASK);
  165. iomd_writeb(0, IOMD_DMAMASK);
  166. for (irq = 0; irq < NR_IRQS; irq++) {
  167. flags = IRQF_VALID;
  168. if (irq <= 6 || (irq >= 9 && irq <= 15) ||
  169. (irq >= 48 && irq <= 55))
  170. flags |= IRQF_PROBE;
  171. switch (irq) {
  172. case 0 ... 7:
  173. set_irq_chip(irq, &clps7500_a_chip);
  174. set_irq_handler(irq, handle_level_irq);
  175. set_irq_flags(irq, flags);
  176. break;
  177. case 8 ... 15:
  178. set_irq_chip(irq, &clps7500_b_chip);
  179. set_irq_handler(irq, handle_level_irq);
  180. set_irq_flags(irq, flags);
  181. break;
  182. case 16 ... 22:
  183. set_irq_chip(irq, &clps7500_dma_chip);
  184. set_irq_handler(irq, handle_level_irq);
  185. set_irq_flags(irq, flags);
  186. break;
  187. case 24 ... 31:
  188. set_irq_chip(irq, &clps7500_c_chip);
  189. set_irq_handler(irq, handle_level_irq);
  190. set_irq_flags(irq, flags);
  191. break;
  192. case 40 ... 47:
  193. set_irq_chip(irq, &clps7500_d_chip);
  194. set_irq_handler(irq, handle_level_irq);
  195. set_irq_flags(irq, flags);
  196. break;
  197. case 48 ... 55:
  198. set_irq_chip(irq, &clps7500_no_chip);
  199. set_irq_handler(irq, handle_level_irq);
  200. set_irq_flags(irq, flags);
  201. break;
  202. case 64 ... 72:
  203. set_irq_chip(irq, &clps7500_fiq_chip);
  204. set_irq_handler(irq, handle_level_irq);
  205. set_irq_flags(irq, flags);
  206. break;
  207. }
  208. }
  209. setup_irq(IRQ_ISA, &irq_isa);
  210. }
  211. static struct map_desc cl7500_io_desc[] __initdata = {
  212. { /* IO space */
  213. .virtual = (unsigned long)IO_BASE,
  214. .pfn = __phys_to_pfn(IO_START),
  215. .length = IO_SIZE,
  216. .type = MT_DEVICE
  217. }, { /* ISA space */
  218. .virtual = ISA_BASE,
  219. .pfn = __phys_to_pfn(ISA_START),
  220. .length = ISA_SIZE,
  221. .type = MT_DEVICE
  222. }, { /* Flash */
  223. .virtual = FLASH_BASE,
  224. .pfn = __phys_to_pfn(FLASH_START),
  225. .length = FLASH_SIZE,
  226. .type = MT_DEVICE
  227. }, { /* LED */
  228. .virtual = LED_BASE,
  229. .pfn = __phys_to_pfn(LED_START),
  230. .length = LED_SIZE,
  231. .type = MT_DEVICE
  232. }
  233. };
  234. static void __init clps7500_map_io(void)
  235. {
  236. iotable_init(cl7500_io_desc, ARRAY_SIZE(cl7500_io_desc));
  237. }
  238. extern void ioctime_init(void);
  239. extern unsigned long ioc_timer_gettimeoffset(void);
  240. static irqreturn_t
  241. clps7500_timer_interrupt(int irq, void *dev_id)
  242. {
  243. write_seqlock(&xtime_lock);
  244. timer_tick();
  245. /* Why not using do_leds interface?? */
  246. {
  247. /* Twinkle the lights. */
  248. static int count, state = 0xff00;
  249. if (count-- == 0) {
  250. state ^= 0x100;
  251. count = 25;
  252. *((volatile unsigned int *)LED_ADDRESS) = state;
  253. }
  254. }
  255. write_sequnlock(&xtime_lock);
  256. return IRQ_HANDLED;
  257. }
  258. static struct irqaction clps7500_timer_irq = {
  259. .name = "CLPS7500 Timer Tick",
  260. .flags = IRQF_DISABLED | IRQF_TIMER,
  261. .handler = clps7500_timer_interrupt,
  262. };
  263. /*
  264. * Set up timer interrupt.
  265. */
  266. static void __init clps7500_timer_init(void)
  267. {
  268. ioctime_init();
  269. setup_irq(IRQ_TIMER, &clps7500_timer_irq);
  270. }
  271. static struct sys_timer clps7500_timer = {
  272. .init = clps7500_timer_init,
  273. .offset = ioc_timer_gettimeoffset,
  274. };
  275. static struct plat_serial8250_port serial_platform_data[] = {
  276. {
  277. .mapbase = 0x03010fe0,
  278. .irq = 10,
  279. .uartclk = 1843200,
  280. .regshift = 2,
  281. .iotype = UPIO_MEM,
  282. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
  283. },
  284. {
  285. .mapbase = 0x03010be0,
  286. .irq = 0,
  287. .uartclk = 1843200,
  288. .regshift = 2,
  289. .iotype = UPIO_MEM,
  290. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
  291. },
  292. {
  293. .iobase = ISASLOT_IO + 0x2e8,
  294. .irq = 41,
  295. .uartclk = 1843200,
  296. .regshift = 0,
  297. .iotype = UPIO_PORT,
  298. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  299. },
  300. {
  301. .iobase = ISASLOT_IO + 0x3e8,
  302. .irq = 40,
  303. .uartclk = 1843200,
  304. .regshift = 0,
  305. .iotype = UPIO_PORT,
  306. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  307. },
  308. { },
  309. };
  310. static struct platform_device serial_device = {
  311. .name = "serial8250",
  312. .id = PLAT8250_DEV_PLATFORM,
  313. .dev = {
  314. .platform_data = serial_platform_data,
  315. },
  316. };
  317. static void __init clps7500_init(void)
  318. {
  319. platform_device_register(&serial_device);
  320. }
  321. MACHINE_START(CLPS7500, "CL-PS7500")
  322. /* Maintainer: Philip Blundell */
  323. .phys_io = 0x03000000,
  324. .io_pg_offst = ((0xe0000000) >> 18) & 0xfffc,
  325. .map_io = clps7500_map_io,
  326. .init_irq = clps7500_init_irq,
  327. .init_machine = clps7500_init,
  328. .timer = &clps7500_timer,
  329. MACHINE_END