iwmmxt.S 7.5 KB

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  1. /*
  2. * linux/arch/arm/kernel/iwmmxt.S
  3. *
  4. * XScale iWMMXt (Concan) context switching and handling
  5. *
  6. * Initial code:
  7. * Copyright (c) 2003, Intel Corporation
  8. *
  9. * Full lazy switching support, optimizations and more, by Nicolas Pitre
  10. * Copyright (c) 2003-2004, MontaVista Software, Inc.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. */
  16. #include <linux/linkage.h>
  17. #include <asm/ptrace.h>
  18. #include <asm/thread_info.h>
  19. #include <asm/asm-offsets.h>
  20. #define MMX_WR0 (0x00)
  21. #define MMX_WR1 (0x08)
  22. #define MMX_WR2 (0x10)
  23. #define MMX_WR3 (0x18)
  24. #define MMX_WR4 (0x20)
  25. #define MMX_WR5 (0x28)
  26. #define MMX_WR6 (0x30)
  27. #define MMX_WR7 (0x38)
  28. #define MMX_WR8 (0x40)
  29. #define MMX_WR9 (0x48)
  30. #define MMX_WR10 (0x50)
  31. #define MMX_WR11 (0x58)
  32. #define MMX_WR12 (0x60)
  33. #define MMX_WR13 (0x68)
  34. #define MMX_WR14 (0x70)
  35. #define MMX_WR15 (0x78)
  36. #define MMX_WCSSF (0x80)
  37. #define MMX_WCASF (0x84)
  38. #define MMX_WCGR0 (0x88)
  39. #define MMX_WCGR1 (0x8C)
  40. #define MMX_WCGR2 (0x90)
  41. #define MMX_WCGR3 (0x94)
  42. #define MMX_SIZE (0x98)
  43. .text
  44. /*
  45. * Lazy switching of Concan coprocessor context
  46. *
  47. * r10 = struct thread_info pointer
  48. * r9 = ret_from_exception
  49. * lr = undefined instr exit
  50. *
  51. * called from prefetch exception handler with interrupts disabled
  52. */
  53. ENTRY(iwmmxt_task_enable)
  54. mrc p15, 0, r2, c15, c1, 0
  55. tst r2, #0x3 @ CP0 and CP1 accessible?
  56. movne pc, lr @ if so no business here
  57. orr r2, r2, #0x3 @ enable access to CP0 and CP1
  58. mcr p15, 0, r2, c15, c1, 0
  59. ldr r3, =concan_owner
  60. add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
  61. ldr r2, [sp, #60] @ current task pc value
  62. ldr r1, [r3] @ get current Concan owner
  63. str r0, [r3] @ this task now owns Concan regs
  64. sub r2, r2, #4 @ adjust pc back
  65. str r2, [sp, #60]
  66. mrc p15, 0, r2, c2, c0, 0
  67. mov r2, r2 @ cpwait
  68. teq r1, #0 @ test for last ownership
  69. mov lr, r9 @ normal exit from exception
  70. beq concan_load @ no owner, skip save
  71. concan_save:
  72. tmrc r2, wCon
  73. @ CUP? wCx
  74. tst r2, #0x1
  75. beq 1f
  76. concan_dump:
  77. wstrw wCSSF, [r1, #MMX_WCSSF]
  78. wstrw wCASF, [r1, #MMX_WCASF]
  79. wstrw wCGR0, [r1, #MMX_WCGR0]
  80. wstrw wCGR1, [r1, #MMX_WCGR1]
  81. wstrw wCGR2, [r1, #MMX_WCGR2]
  82. wstrw wCGR3, [r1, #MMX_WCGR3]
  83. 1: @ MUP? wRn
  84. tst r2, #0x2
  85. beq 2f
  86. wstrd wR0, [r1, #MMX_WR0]
  87. wstrd wR1, [r1, #MMX_WR1]
  88. wstrd wR2, [r1, #MMX_WR2]
  89. wstrd wR3, [r1, #MMX_WR3]
  90. wstrd wR4, [r1, #MMX_WR4]
  91. wstrd wR5, [r1, #MMX_WR5]
  92. wstrd wR6, [r1, #MMX_WR6]
  93. wstrd wR7, [r1, #MMX_WR7]
  94. wstrd wR8, [r1, #MMX_WR8]
  95. wstrd wR9, [r1, #MMX_WR9]
  96. wstrd wR10, [r1, #MMX_WR10]
  97. wstrd wR11, [r1, #MMX_WR11]
  98. wstrd wR12, [r1, #MMX_WR12]
  99. wstrd wR13, [r1, #MMX_WR13]
  100. wstrd wR14, [r1, #MMX_WR14]
  101. wstrd wR15, [r1, #MMX_WR15]
  102. 2: teq r0, #0 @ anything to load?
  103. moveq pc, lr
  104. concan_load:
  105. @ Load wRn
  106. wldrd wR0, [r0, #MMX_WR0]
  107. wldrd wR1, [r0, #MMX_WR1]
  108. wldrd wR2, [r0, #MMX_WR2]
  109. wldrd wR3, [r0, #MMX_WR3]
  110. wldrd wR4, [r0, #MMX_WR4]
  111. wldrd wR5, [r0, #MMX_WR5]
  112. wldrd wR6, [r0, #MMX_WR6]
  113. wldrd wR7, [r0, #MMX_WR7]
  114. wldrd wR8, [r0, #MMX_WR8]
  115. wldrd wR9, [r0, #MMX_WR9]
  116. wldrd wR10, [r0, #MMX_WR10]
  117. wldrd wR11, [r0, #MMX_WR11]
  118. wldrd wR12, [r0, #MMX_WR12]
  119. wldrd wR13, [r0, #MMX_WR13]
  120. wldrd wR14, [r0, #MMX_WR14]
  121. wldrd wR15, [r0, #MMX_WR15]
  122. @ Load wCx
  123. wldrw wCSSF, [r0, #MMX_WCSSF]
  124. wldrw wCASF, [r0, #MMX_WCASF]
  125. wldrw wCGR0, [r0, #MMX_WCGR0]
  126. wldrw wCGR1, [r0, #MMX_WCGR1]
  127. wldrw wCGR2, [r0, #MMX_WCGR2]
  128. wldrw wCGR3, [r0, #MMX_WCGR3]
  129. @ clear CUP/MUP (only if r1 != 0)
  130. teq r1, #0
  131. mov r2, #0
  132. moveq pc, lr
  133. tmcr wCon, r2
  134. mov pc, lr
  135. /*
  136. * Back up Concan regs to save area and disable access to them
  137. * (mainly for gdb or sleep mode usage)
  138. *
  139. * r0 = struct thread_info pointer of target task or NULL for any
  140. */
  141. ENTRY(iwmmxt_task_disable)
  142. stmfd sp!, {r4, lr}
  143. mrs ip, cpsr
  144. orr r2, ip, #PSR_I_BIT @ disable interrupts
  145. msr cpsr_c, r2
  146. ldr r3, =concan_owner
  147. add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
  148. ldr r1, [r3] @ get current Concan owner
  149. teq r1, #0 @ any current owner?
  150. beq 1f @ no: quit
  151. teq r0, #0 @ any owner?
  152. teqne r1, r2 @ or specified one?
  153. bne 1f @ no: quit
  154. mrc p15, 0, r4, c15, c1, 0
  155. orr r4, r4, #0x3 @ enable access to CP0 and CP1
  156. mcr p15, 0, r4, c15, c1, 0
  157. mov r0, #0 @ nothing to load
  158. str r0, [r3] @ no more current owner
  159. mrc p15, 0, r2, c2, c0, 0
  160. mov r2, r2 @ cpwait
  161. bl concan_save
  162. bic r4, r4, #0x3 @ disable access to CP0 and CP1
  163. mcr p15, 0, r4, c15, c1, 0
  164. mrc p15, 0, r2, c2, c0, 0
  165. mov r2, r2 @ cpwait
  166. 1: msr cpsr_c, ip @ restore interrupt mode
  167. ldmfd sp!, {r4, pc}
  168. /*
  169. * Copy Concan state to given memory address
  170. *
  171. * r0 = struct thread_info pointer of target task
  172. * r1 = memory address where to store Concan state
  173. *
  174. * this is called mainly in the creation of signal stack frames
  175. */
  176. ENTRY(iwmmxt_task_copy)
  177. mrs ip, cpsr
  178. orr r2, ip, #PSR_I_BIT @ disable interrupts
  179. msr cpsr_c, r2
  180. ldr r3, =concan_owner
  181. add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
  182. ldr r3, [r3] @ get current Concan owner
  183. teq r2, r3 @ does this task own it...
  184. beq 1f
  185. @ current Concan values are in the task save area
  186. msr cpsr_c, ip @ restore interrupt mode
  187. mov r0, r1
  188. mov r1, r2
  189. mov r2, #MMX_SIZE
  190. b memcpy
  191. 1: @ this task owns Concan regs -- grab a copy from there
  192. mov r0, #0 @ nothing to load
  193. mov r2, #3 @ save all regs
  194. mov r3, lr @ preserve return address
  195. bl concan_dump
  196. msr cpsr_c, ip @ restore interrupt mode
  197. mov pc, r3
  198. /*
  199. * Restore Concan state from given memory address
  200. *
  201. * r0 = struct thread_info pointer of target task
  202. * r1 = memory address where to get Concan state from
  203. *
  204. * this is used to restore Concan state when unwinding a signal stack frame
  205. */
  206. ENTRY(iwmmxt_task_restore)
  207. mrs ip, cpsr
  208. orr r2, ip, #PSR_I_BIT @ disable interrupts
  209. msr cpsr_c, r2
  210. ldr r3, =concan_owner
  211. add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
  212. ldr r3, [r3] @ get current Concan owner
  213. bic r2, r2, #0x7 @ 64-bit alignment
  214. teq r2, r3 @ does this task own it...
  215. beq 1f
  216. @ this task doesn't own Concan regs -- use its save area
  217. msr cpsr_c, ip @ restore interrupt mode
  218. mov r0, r2
  219. mov r2, #MMX_SIZE
  220. b memcpy
  221. 1: @ this task owns Concan regs -- load them directly
  222. mov r0, r1
  223. mov r1, #0 @ don't clear CUP/MUP
  224. mov r3, lr @ preserve return address
  225. bl concan_load
  226. msr cpsr_c, ip @ restore interrupt mode
  227. mov pc, r3
  228. /*
  229. * Concan handling on task switch
  230. *
  231. * r0 = next thread_info pointer
  232. *
  233. * Called only from the iwmmxt notifier with task preemption disabled.
  234. */
  235. ENTRY(iwmmxt_task_switch)
  236. mrc p15, 0, r1, c15, c1, 0
  237. tst r1, #0x3 @ CP0 and CP1 accessible?
  238. bne 1f @ yes: block them for next task
  239. ldr r2, =concan_owner
  240. add r3, r0, #TI_IWMMXT_STATE @ get next task Concan save area
  241. ldr r2, [r2] @ get current Concan owner
  242. teq r2, r3 @ next task owns it?
  243. movne pc, lr @ no: leave Concan disabled
  244. 1: eor r1, r1, #3 @ flip Concan access
  245. mcr p15, 0, r1, c15, c1, 0
  246. mrc p15, 0, r1, c2, c0, 0
  247. sub pc, lr, r1, lsr #32 @ cpwait and return
  248. /*
  249. * Remove Concan ownership of given task
  250. *
  251. * r0 = struct thread_info pointer
  252. */
  253. ENTRY(iwmmxt_task_release)
  254. mrs r2, cpsr
  255. orr ip, r2, #PSR_I_BIT @ disable interrupts
  256. msr cpsr_c, ip
  257. ldr r3, =concan_owner
  258. add r0, r0, #TI_IWMMXT_STATE @ get task Concan save area
  259. ldr r1, [r3] @ get current Concan owner
  260. eors r0, r0, r1 @ if equal...
  261. streq r0, [r3] @ then clear ownership
  262. msr cpsr_c, r2 @ restore interrupts
  263. mov pc, lr
  264. .data
  265. concan_owner:
  266. .word 0