head.S 8.7 KB

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  1. /*
  2. * linux/arch/arm/kernel/head.S
  3. *
  4. * Copyright (C) 1994-2002 Russell King
  5. * Copyright (c) 2003 ARM Limited
  6. * All Rights Reserved
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * Kernel startup code for all 32-bit CPUs
  13. */
  14. #include <linux/linkage.h>
  15. #include <linux/init.h>
  16. #include <asm/assembler.h>
  17. #include <asm/domain.h>
  18. #include <asm/ptrace.h>
  19. #include <asm/asm-offsets.h>
  20. #include <asm/memory.h>
  21. #include <asm/thread_info.h>
  22. #include <asm/system.h>
  23. #if (PHYS_OFFSET & 0x001fffff)
  24. #error "PHYS_OFFSET must be at an even 2MiB boundary!"
  25. #endif
  26. #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
  27. #define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET)
  28. /*
  29. * swapper_pg_dir is the virtual address of the initial page table.
  30. * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
  31. * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
  32. * the least significant 16 bits to be 0x8000, but we could probably
  33. * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
  34. */
  35. #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
  36. #error KERNEL_RAM_VADDR must start at 0xXXXX8000
  37. #endif
  38. .globl swapper_pg_dir
  39. .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
  40. .macro pgtbl, rd
  41. ldr \rd, =(KERNEL_RAM_PADDR - 0x4000)
  42. .endm
  43. #ifdef CONFIG_XIP_KERNEL
  44. #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
  45. #define KERNEL_END _edata_loc
  46. #else
  47. #define KERNEL_START KERNEL_RAM_VADDR
  48. #define KERNEL_END _end
  49. #endif
  50. /*
  51. * Kernel startup entry point.
  52. * ---------------------------
  53. *
  54. * This is normally called from the decompressor code. The requirements
  55. * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
  56. * r1 = machine nr.
  57. *
  58. * This code is mostly position independent, so if you link the kernel at
  59. * 0xc0008000, you call this at __pa(0xc0008000).
  60. *
  61. * See linux/arch/arm/tools/mach-types for the complete list of machine
  62. * numbers for r1.
  63. *
  64. * We're trying to keep crap to a minimum; DO NOT add any machine specific
  65. * crap here - that's what the boot loader (or in extreme, well justified
  66. * circumstances, zImage) is for.
  67. */
  68. __INIT
  69. .type stext, %function
  70. ENTRY(stext)
  71. msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
  72. @ and irqs disabled
  73. mrc p15, 0, r9, c0, c0 @ get processor id
  74. bl __lookup_processor_type @ r5=procinfo r9=cpuid
  75. movs r10, r5 @ invalid processor (r5=0)?
  76. beq __error_p @ yes, error 'p'
  77. bl __lookup_machine_type @ r5=machinfo
  78. movs r8, r5 @ invalid machine (r5=0)?
  79. beq __error_a @ yes, error 'a'
  80. bl __create_page_tables
  81. /*
  82. * The following calls CPU specific code in a position independent
  83. * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
  84. * xxx_proc_info structure selected by __lookup_machine_type
  85. * above. On return, the CPU will be ready for the MMU to be
  86. * turned on, and r0 will hold the CPU control register value.
  87. */
  88. ldr r13, __switch_data @ address to jump to after
  89. @ mmu has been enabled
  90. adr lr, __enable_mmu @ return (PIC) address
  91. add pc, r10, #PROCINFO_INITFUNC
  92. #if defined(CONFIG_SMP)
  93. .type secondary_startup, #function
  94. ENTRY(secondary_startup)
  95. /*
  96. * Common entry point for secondary CPUs.
  97. *
  98. * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
  99. * the processor type - there is no need to check the machine type
  100. * as it has already been validated by the primary processor.
  101. */
  102. msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  103. mrc p15, 0, r9, c0, c0 @ get processor id
  104. bl __lookup_processor_type
  105. movs r10, r5 @ invalid processor?
  106. moveq r0, #'p' @ yes, error 'p'
  107. beq __error
  108. /*
  109. * Use the page tables supplied from __cpu_up.
  110. */
  111. adr r4, __secondary_data
  112. ldmia r4, {r5, r7, r13} @ address to jump to after
  113. sub r4, r4, r5 @ mmu has been enabled
  114. ldr r4, [r7, r4] @ get secondary_data.pgdir
  115. adr lr, __enable_mmu @ return address
  116. add pc, r10, #PROCINFO_INITFUNC @ initialise processor
  117. @ (return control reg)
  118. /*
  119. * r6 = &secondary_data
  120. */
  121. ENTRY(__secondary_switched)
  122. ldr sp, [r7, #4] @ get secondary_data.stack
  123. mov fp, #0
  124. b secondary_start_kernel
  125. .type __secondary_data, %object
  126. __secondary_data:
  127. .long .
  128. .long secondary_data
  129. .long __secondary_switched
  130. #endif /* defined(CONFIG_SMP) */
  131. /*
  132. * Setup common bits before finally enabling the MMU. Essentially
  133. * this is just loading the page table pointer and domain access
  134. * registers.
  135. */
  136. .type __enable_mmu, %function
  137. __enable_mmu:
  138. #ifdef CONFIG_ALIGNMENT_TRAP
  139. orr r0, r0, #CR_A
  140. #else
  141. bic r0, r0, #CR_A
  142. #endif
  143. #ifdef CONFIG_CPU_DCACHE_DISABLE
  144. bic r0, r0, #CR_C
  145. #endif
  146. #ifdef CONFIG_CPU_BPREDICT_DISABLE
  147. bic r0, r0, #CR_Z
  148. #endif
  149. #ifdef CONFIG_CPU_ICACHE_DISABLE
  150. bic r0, r0, #CR_I
  151. #endif
  152. mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
  153. domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
  154. domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
  155. domain_val(DOMAIN_IO, DOMAIN_CLIENT))
  156. mcr p15, 0, r5, c3, c0, 0 @ load domain access register
  157. mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
  158. b __turn_mmu_on
  159. /*
  160. * Enable the MMU. This completely changes the structure of the visible
  161. * memory space. You will not be able to trace execution through this.
  162. * If you have an enquiry about this, *please* check the linux-arm-kernel
  163. * mailing list archives BEFORE sending another post to the list.
  164. *
  165. * r0 = cp#15 control register
  166. * r13 = *virtual* address to jump to upon completion
  167. *
  168. * other registers depend on the function called upon completion
  169. */
  170. .align 5
  171. .type __turn_mmu_on, %function
  172. __turn_mmu_on:
  173. mov r0, r0
  174. mcr p15, 0, r0, c1, c0, 0 @ write control reg
  175. mrc p15, 0, r3, c0, c0, 0 @ read id reg
  176. mov r3, r3
  177. mov r3, r3
  178. mov pc, r13
  179. /*
  180. * Setup the initial page tables. We only setup the barest
  181. * amount which are required to get the kernel running, which
  182. * generally means mapping in the kernel code.
  183. *
  184. * r8 = machinfo
  185. * r9 = cpuid
  186. * r10 = procinfo
  187. *
  188. * Returns:
  189. * r0, r3, r6, r7 corrupted
  190. * r4 = physical page table address
  191. */
  192. .type __create_page_tables, %function
  193. __create_page_tables:
  194. pgtbl r4 @ page table address
  195. /*
  196. * Clear the 16K level 1 swapper page table
  197. */
  198. mov r0, r4
  199. mov r3, #0
  200. add r6, r0, #0x4000
  201. 1: str r3, [r0], #4
  202. str r3, [r0], #4
  203. str r3, [r0], #4
  204. str r3, [r0], #4
  205. teq r0, r6
  206. bne 1b
  207. ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
  208. /*
  209. * Create identity mapping for first MB of kernel to
  210. * cater for the MMU enable. This identity mapping
  211. * will be removed by paging_init(). We use our current program
  212. * counter to determine corresponding section base address.
  213. */
  214. mov r6, pc, lsr #20 @ start of kernel section
  215. orr r3, r7, r6, lsl #20 @ flags + kernel base
  216. str r3, [r4, r6, lsl #2] @ identity mapping
  217. /*
  218. * Now setup the pagetables for our kernel direct
  219. * mapped region.
  220. */
  221. add r0, r4, #(KERNEL_START & 0xff000000) >> 18
  222. str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]!
  223. ldr r6, =(KERNEL_END - 1)
  224. add r0, r0, #4
  225. add r6, r4, r6, lsr #18
  226. 1: cmp r0, r6
  227. add r3, r3, #1 << 20
  228. strls r3, [r0], #4
  229. bls 1b
  230. #ifdef CONFIG_XIP_KERNEL
  231. /*
  232. * Map some ram to cover our .data and .bss areas.
  233. */
  234. orr r3, r7, #(KERNEL_RAM_PADDR & 0xff000000)
  235. orr r3, r3, #(KERNEL_RAM_PADDR & 0x00f00000)
  236. add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18
  237. str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]!
  238. ldr r6, =(_end - 1)
  239. add r0, r0, #4
  240. add r6, r4, r6, lsr #18
  241. 1: cmp r0, r6
  242. add r3, r3, #1 << 20
  243. strls r3, [r0], #4
  244. bls 1b
  245. #endif
  246. /*
  247. * Then map first 1MB of ram in case it contains our boot params.
  248. */
  249. add r0, r4, #PAGE_OFFSET >> 18
  250. orr r6, r7, #(PHYS_OFFSET & 0xff000000)
  251. orr r6, r6, #(PHYS_OFFSET & 0x00e00000)
  252. str r6, [r0]
  253. #ifdef CONFIG_DEBUG_LL
  254. ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
  255. /*
  256. * Map in IO space for serial debugging.
  257. * This allows debug messages to be output
  258. * via a serial console before paging_init.
  259. */
  260. ldr r3, [r8, #MACHINFO_PGOFFIO]
  261. add r0, r4, r3
  262. rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
  263. cmp r3, #0x0800 @ limit to 512MB
  264. movhi r3, #0x0800
  265. add r6, r0, r3
  266. ldr r3, [r8, #MACHINFO_PHYSIO]
  267. orr r3, r3, r7
  268. 1: str r3, [r0], #4
  269. add r3, r3, #1 << 20
  270. teq r0, r6
  271. bne 1b
  272. #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
  273. /*
  274. * If we're using the NetWinder or CATS, we also need to map
  275. * in the 16550-type serial port for the debug messages
  276. */
  277. add r0, r4, #0xff000000 >> 18
  278. orr r3, r7, #0x7c000000
  279. str r3, [r0]
  280. #endif
  281. #ifdef CONFIG_ARCH_RPC
  282. /*
  283. * Map in screen at 0x02000000 & SCREEN2_BASE
  284. * Similar reasons here - for debug. This is
  285. * only for Acorn RiscPC architectures.
  286. */
  287. add r0, r4, #0x02000000 >> 18
  288. orr r3, r7, #0x02000000
  289. str r3, [r0]
  290. add r0, r4, #0xd8000000 >> 18
  291. str r3, [r0]
  292. #endif
  293. #endif
  294. mov pc, lr
  295. .ltorg
  296. #include "head-common.S"