dma-isa.c 5.1 KB

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  1. /*
  2. * linux/arch/arm/kernel/dma-isa.c
  3. *
  4. * Copyright (C) 1999-2000 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * ISA DMA primitives
  11. * Taken from various sources, including:
  12. * linux/include/asm/dma.h: Defines for using and allocating dma channels.
  13. * Written by Hennus Bergman, 1992.
  14. * High DMA channel support & info by Hannu Savolainen and John Boyd,
  15. * Nov. 1992.
  16. * arch/arm/kernel/dma-ebsa285.c
  17. * Copyright (C) 1998 Phil Blundell
  18. */
  19. #include <linux/ioport.h>
  20. #include <linux/init.h>
  21. #include <linux/dma-mapping.h>
  22. #include <asm/dma.h>
  23. #include <asm/io.h>
  24. #include <asm/mach/dma.h>
  25. #define ISA_DMA_MODE_READ 0x44
  26. #define ISA_DMA_MODE_WRITE 0x48
  27. #define ISA_DMA_MODE_CASCADE 0xc0
  28. #define ISA_DMA_AUTOINIT 0x10
  29. #define ISA_DMA_MASK 0
  30. #define ISA_DMA_MODE 1
  31. #define ISA_DMA_CLRFF 2
  32. #define ISA_DMA_PGHI 3
  33. #define ISA_DMA_PGLO 4
  34. #define ISA_DMA_ADDR 5
  35. #define ISA_DMA_COUNT 6
  36. static unsigned int isa_dma_port[8][7] = {
  37. /* MASK MODE CLRFF PAGE_HI PAGE_LO ADDR COUNT */
  38. { 0x0a, 0x0b, 0x0c, 0x487, 0x087, 0x00, 0x01 },
  39. { 0x0a, 0x0b, 0x0c, 0x483, 0x083, 0x02, 0x03 },
  40. { 0x0a, 0x0b, 0x0c, 0x481, 0x081, 0x04, 0x05 },
  41. { 0x0a, 0x0b, 0x0c, 0x482, 0x082, 0x06, 0x07 },
  42. { 0xd4, 0xd6, 0xd8, 0x000, 0x000, 0xc0, 0xc2 },
  43. { 0xd4, 0xd6, 0xd8, 0x48b, 0x08b, 0xc4, 0xc6 },
  44. { 0xd4, 0xd6, 0xd8, 0x489, 0x089, 0xc8, 0xca },
  45. { 0xd4, 0xd6, 0xd8, 0x48a, 0x08a, 0xcc, 0xce }
  46. };
  47. static int isa_get_dma_residue(dmach_t channel, dma_t *dma)
  48. {
  49. unsigned int io_port = isa_dma_port[channel][ISA_DMA_COUNT];
  50. int count;
  51. count = 1 + inb(io_port);
  52. count |= inb(io_port) << 8;
  53. return channel < 4 ? count : (count << 1);
  54. }
  55. static void isa_enable_dma(dmach_t channel, dma_t *dma)
  56. {
  57. if (dma->invalid) {
  58. unsigned long address, length;
  59. unsigned int mode;
  60. enum dma_data_direction direction;
  61. mode = channel & 3;
  62. switch (dma->dma_mode & DMA_MODE_MASK) {
  63. case DMA_MODE_READ:
  64. mode |= ISA_DMA_MODE_READ;
  65. direction = DMA_FROM_DEVICE;
  66. break;
  67. case DMA_MODE_WRITE:
  68. mode |= ISA_DMA_MODE_WRITE;
  69. direction = DMA_TO_DEVICE;
  70. break;
  71. case DMA_MODE_CASCADE:
  72. mode |= ISA_DMA_MODE_CASCADE;
  73. direction = DMA_BIDIRECTIONAL;
  74. break;
  75. default:
  76. direction = DMA_NONE;
  77. break;
  78. }
  79. if (!dma->sg) {
  80. /*
  81. * Cope with ISA-style drivers which expect cache
  82. * coherence.
  83. */
  84. dma->sg = &dma->buf;
  85. dma->sgcount = 1;
  86. dma->buf.length = dma->count;
  87. dma->buf.dma_address = dma_map_single(NULL,
  88. dma->addr, dma->count,
  89. direction);
  90. }
  91. address = dma->buf.dma_address;
  92. length = dma->buf.length - 1;
  93. outb(address >> 16, isa_dma_port[channel][ISA_DMA_PGLO]);
  94. outb(address >> 24, isa_dma_port[channel][ISA_DMA_PGHI]);
  95. if (channel >= 4) {
  96. address >>= 1;
  97. length >>= 1;
  98. }
  99. outb(0, isa_dma_port[channel][ISA_DMA_CLRFF]);
  100. outb(address, isa_dma_port[channel][ISA_DMA_ADDR]);
  101. outb(address >> 8, isa_dma_port[channel][ISA_DMA_ADDR]);
  102. outb(length, isa_dma_port[channel][ISA_DMA_COUNT]);
  103. outb(length >> 8, isa_dma_port[channel][ISA_DMA_COUNT]);
  104. if (dma->dma_mode & DMA_AUTOINIT)
  105. mode |= ISA_DMA_AUTOINIT;
  106. outb(mode, isa_dma_port[channel][ISA_DMA_MODE]);
  107. dma->invalid = 0;
  108. }
  109. outb(channel & 3, isa_dma_port[channel][ISA_DMA_MASK]);
  110. }
  111. static void isa_disable_dma(dmach_t channel, dma_t *dma)
  112. {
  113. outb(channel | 4, isa_dma_port[channel][ISA_DMA_MASK]);
  114. }
  115. static struct dma_ops isa_dma_ops = {
  116. .type = "ISA",
  117. .enable = isa_enable_dma,
  118. .disable = isa_disable_dma,
  119. .residue = isa_get_dma_residue,
  120. };
  121. static struct resource dma_resources[] = { {
  122. .name = "dma1",
  123. .start = 0x0000,
  124. .end = 0x000f
  125. }, {
  126. .name = "dma low page",
  127. .start = 0x0080,
  128. .end = 0x008f
  129. }, {
  130. .name = "dma2",
  131. .start = 0x00c0,
  132. .end = 0x00df
  133. }, {
  134. .name = "dma high page",
  135. .start = 0x0480,
  136. .end = 0x048f
  137. } };
  138. void __init isa_init_dma(dma_t *dma)
  139. {
  140. /*
  141. * Try to autodetect presence of an ISA DMA controller.
  142. * We do some minimal initialisation, and check that
  143. * channel 0's DMA address registers are writeable.
  144. */
  145. outb(0xff, 0x0d);
  146. outb(0xff, 0xda);
  147. /*
  148. * Write high and low address, and then read them back
  149. * in the same order.
  150. */
  151. outb(0x55, 0x00);
  152. outb(0xaa, 0x00);
  153. if (inb(0) == 0x55 && inb(0) == 0xaa) {
  154. int channel, i;
  155. for (channel = 0; channel < 8; channel++) {
  156. dma[channel].d_ops = &isa_dma_ops;
  157. isa_disable_dma(channel, NULL);
  158. }
  159. outb(0x40, 0x0b);
  160. outb(0x41, 0x0b);
  161. outb(0x42, 0x0b);
  162. outb(0x43, 0x0b);
  163. outb(0xc0, 0xd6);
  164. outb(0x41, 0xd6);
  165. outb(0x42, 0xd6);
  166. outb(0x43, 0xd6);
  167. outb(0, 0xd4);
  168. outb(0x10, 0x08);
  169. outb(0x10, 0xd0);
  170. /*
  171. * Is this correct? According to my documentation, it
  172. * doesn't appear to be. It should be:
  173. * outb(0x3f, 0x40b); outb(0x3f, 0x4d6);
  174. */
  175. outb(0x30, 0x40b);
  176. outb(0x31, 0x40b);
  177. outb(0x32, 0x40b);
  178. outb(0x33, 0x40b);
  179. outb(0x31, 0x4d6);
  180. outb(0x32, 0x4d6);
  181. outb(0x33, 0x4d6);
  182. request_dma(DMA_ISA_CASCADE, "cascade");
  183. for (i = 0; i < sizeof(dma_resources) / sizeof(dma_resources[0]); i++)
  184. request_resource(&ioport_resource, dma_resources + i);
  185. }
  186. }