crunch-bits.S 8.3 KB

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  1. /*
  2. * arch/arm/kernel/crunch-bits.S
  3. * Cirrus MaverickCrunch context switching and handling
  4. *
  5. * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
  6. *
  7. * Shamelessly stolen from the iWMMXt code by Nicolas Pitre, which is
  8. * Copyright (c) 2003-2004, MontaVista Software, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/linkage.h>
  15. #include <asm/ptrace.h>
  16. #include <asm/thread_info.h>
  17. #include <asm/asm-offsets.h>
  18. #include <asm/arch/ep93xx-regs.h>
  19. /*
  20. * We can't use hex constants here due to a bug in gas.
  21. */
  22. #define CRUNCH_MVDX0 0
  23. #define CRUNCH_MVDX1 8
  24. #define CRUNCH_MVDX2 16
  25. #define CRUNCH_MVDX3 24
  26. #define CRUNCH_MVDX4 32
  27. #define CRUNCH_MVDX5 40
  28. #define CRUNCH_MVDX6 48
  29. #define CRUNCH_MVDX7 56
  30. #define CRUNCH_MVDX8 64
  31. #define CRUNCH_MVDX9 72
  32. #define CRUNCH_MVDX10 80
  33. #define CRUNCH_MVDX11 88
  34. #define CRUNCH_MVDX12 96
  35. #define CRUNCH_MVDX13 104
  36. #define CRUNCH_MVDX14 112
  37. #define CRUNCH_MVDX15 120
  38. #define CRUNCH_MVAX0L 128
  39. #define CRUNCH_MVAX0M 132
  40. #define CRUNCH_MVAX0H 136
  41. #define CRUNCH_MVAX1L 140
  42. #define CRUNCH_MVAX1M 144
  43. #define CRUNCH_MVAX1H 148
  44. #define CRUNCH_MVAX2L 152
  45. #define CRUNCH_MVAX2M 156
  46. #define CRUNCH_MVAX2H 160
  47. #define CRUNCH_MVAX3L 164
  48. #define CRUNCH_MVAX3M 168
  49. #define CRUNCH_MVAX3H 172
  50. #define CRUNCH_DSPSC 176
  51. #define CRUNCH_SIZE 184
  52. .text
  53. /*
  54. * Lazy switching of crunch coprocessor context
  55. *
  56. * r10 = struct thread_info pointer
  57. * r9 = ret_from_exception
  58. * lr = undefined instr exit
  59. *
  60. * called from prefetch exception handler with interrupts disabled
  61. */
  62. ENTRY(crunch_task_enable)
  63. ldr r8, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr
  64. ldr r1, [r8, #0x80]
  65. tst r1, #0x00800000 @ access to crunch enabled?
  66. movne pc, lr @ if so no business here
  67. mov r3, #0xaa @ unlock syscon swlock
  68. str r3, [r8, #0xc0]
  69. orr r1, r1, #0x00800000 @ enable access to crunch
  70. str r1, [r8, #0x80]
  71. ldr r3, =crunch_owner
  72. add r0, r10, #TI_CRUNCH_STATE @ get task crunch save area
  73. ldr r2, [sp, #60] @ current task pc value
  74. ldr r1, [r3] @ get current crunch owner
  75. str r0, [r3] @ this task now owns crunch
  76. sub r2, r2, #4 @ adjust pc back
  77. str r2, [sp, #60]
  78. ldr r2, [r8, #0x80]
  79. mov r2, r2 @ flush out enable (@@@)
  80. teq r1, #0 @ test for last ownership
  81. mov lr, r9 @ normal exit from exception
  82. beq crunch_load @ no owner, skip save
  83. crunch_save:
  84. cfstr64 mvdx0, [r1, #CRUNCH_MVDX0] @ save 64b registers
  85. cfstr64 mvdx1, [r1, #CRUNCH_MVDX1]
  86. cfstr64 mvdx2, [r1, #CRUNCH_MVDX2]
  87. cfstr64 mvdx3, [r1, #CRUNCH_MVDX3]
  88. cfstr64 mvdx4, [r1, #CRUNCH_MVDX4]
  89. cfstr64 mvdx5, [r1, #CRUNCH_MVDX5]
  90. cfstr64 mvdx6, [r1, #CRUNCH_MVDX6]
  91. cfstr64 mvdx7, [r1, #CRUNCH_MVDX7]
  92. cfstr64 mvdx8, [r1, #CRUNCH_MVDX8]
  93. cfstr64 mvdx9, [r1, #CRUNCH_MVDX9]
  94. cfstr64 mvdx10, [r1, #CRUNCH_MVDX10]
  95. cfstr64 mvdx11, [r1, #CRUNCH_MVDX11]
  96. cfstr64 mvdx12, [r1, #CRUNCH_MVDX12]
  97. cfstr64 mvdx13, [r1, #CRUNCH_MVDX13]
  98. cfstr64 mvdx14, [r1, #CRUNCH_MVDX14]
  99. cfstr64 mvdx15, [r1, #CRUNCH_MVDX15]
  100. #ifdef __ARMEB__
  101. #error fix me for ARMEB
  102. #endif
  103. cfmv32al mvfx0, mvax0 @ save 72b accumulators
  104. cfstr32 mvfx0, [r1, #CRUNCH_MVAX0L]
  105. cfmv32am mvfx0, mvax0
  106. cfstr32 mvfx0, [r1, #CRUNCH_MVAX0M]
  107. cfmv32ah mvfx0, mvax0
  108. cfstr32 mvfx0, [r1, #CRUNCH_MVAX0H]
  109. cfmv32al mvfx0, mvax1
  110. cfstr32 mvfx0, [r1, #CRUNCH_MVAX1L]
  111. cfmv32am mvfx0, mvax1
  112. cfstr32 mvfx0, [r1, #CRUNCH_MVAX1M]
  113. cfmv32ah mvfx0, mvax1
  114. cfstr32 mvfx0, [r1, #CRUNCH_MVAX1H]
  115. cfmv32al mvfx0, mvax2
  116. cfstr32 mvfx0, [r1, #CRUNCH_MVAX2L]
  117. cfmv32am mvfx0, mvax2
  118. cfstr32 mvfx0, [r1, #CRUNCH_MVAX2M]
  119. cfmv32ah mvfx0, mvax2
  120. cfstr32 mvfx0, [r1, #CRUNCH_MVAX2H]
  121. cfmv32al mvfx0, mvax3
  122. cfstr32 mvfx0, [r1, #CRUNCH_MVAX3L]
  123. cfmv32am mvfx0, mvax3
  124. cfstr32 mvfx0, [r1, #CRUNCH_MVAX3M]
  125. cfmv32ah mvfx0, mvax3
  126. cfstr32 mvfx0, [r1, #CRUNCH_MVAX3H]
  127. cfmv32sc mvdx0, dspsc @ save status word
  128. cfstr64 mvdx0, [r1, #CRUNCH_DSPSC]
  129. teq r0, #0 @ anything to load?
  130. cfldr64eq mvdx0, [r1, #CRUNCH_MVDX0] @ mvdx0 was clobbered
  131. moveq pc, lr
  132. crunch_load:
  133. cfldr64 mvdx0, [r0, #CRUNCH_DSPSC] @ load status word
  134. cfmvsc32 dspsc, mvdx0
  135. cfldr32 mvfx0, [r0, #CRUNCH_MVAX0L] @ load 72b accumulators
  136. cfmval32 mvax0, mvfx0
  137. cfldr32 mvfx0, [r0, #CRUNCH_MVAX0M]
  138. cfmvam32 mvax0, mvfx0
  139. cfldr32 mvfx0, [r0, #CRUNCH_MVAX0H]
  140. cfmvah32 mvax0, mvfx0
  141. cfldr32 mvfx0, [r0, #CRUNCH_MVAX1L]
  142. cfmval32 mvax1, mvfx0
  143. cfldr32 mvfx0, [r0, #CRUNCH_MVAX1M]
  144. cfmvam32 mvax1, mvfx0
  145. cfldr32 mvfx0, [r0, #CRUNCH_MVAX1H]
  146. cfmvah32 mvax1, mvfx0
  147. cfldr32 mvfx0, [r0, #CRUNCH_MVAX2L]
  148. cfmval32 mvax2, mvfx0
  149. cfldr32 mvfx0, [r0, #CRUNCH_MVAX2M]
  150. cfmvam32 mvax2, mvfx0
  151. cfldr32 mvfx0, [r0, #CRUNCH_MVAX2H]
  152. cfmvah32 mvax2, mvfx0
  153. cfldr32 mvfx0, [r0, #CRUNCH_MVAX3L]
  154. cfmval32 mvax3, mvfx0
  155. cfldr32 mvfx0, [r0, #CRUNCH_MVAX3M]
  156. cfmvam32 mvax3, mvfx0
  157. cfldr32 mvfx0, [r0, #CRUNCH_MVAX3H]
  158. cfmvah32 mvax3, mvfx0
  159. cfldr64 mvdx0, [r0, #CRUNCH_MVDX0] @ load 64b registers
  160. cfldr64 mvdx1, [r0, #CRUNCH_MVDX1]
  161. cfldr64 mvdx2, [r0, #CRUNCH_MVDX2]
  162. cfldr64 mvdx3, [r0, #CRUNCH_MVDX3]
  163. cfldr64 mvdx4, [r0, #CRUNCH_MVDX4]
  164. cfldr64 mvdx5, [r0, #CRUNCH_MVDX5]
  165. cfldr64 mvdx6, [r0, #CRUNCH_MVDX6]
  166. cfldr64 mvdx7, [r0, #CRUNCH_MVDX7]
  167. cfldr64 mvdx8, [r0, #CRUNCH_MVDX8]
  168. cfldr64 mvdx9, [r0, #CRUNCH_MVDX9]
  169. cfldr64 mvdx10, [r0, #CRUNCH_MVDX10]
  170. cfldr64 mvdx11, [r0, #CRUNCH_MVDX11]
  171. cfldr64 mvdx12, [r0, #CRUNCH_MVDX12]
  172. cfldr64 mvdx13, [r0, #CRUNCH_MVDX13]
  173. cfldr64 mvdx14, [r0, #CRUNCH_MVDX14]
  174. cfldr64 mvdx15, [r0, #CRUNCH_MVDX15]
  175. mov pc, lr
  176. /*
  177. * Back up crunch regs to save area and disable access to them
  178. * (mainly for gdb or sleep mode usage)
  179. *
  180. * r0 = struct thread_info pointer of target task or NULL for any
  181. */
  182. ENTRY(crunch_task_disable)
  183. stmfd sp!, {r4, r5, lr}
  184. mrs ip, cpsr
  185. orr r2, ip, #PSR_I_BIT @ disable interrupts
  186. msr cpsr_c, r2
  187. ldr r4, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr
  188. ldr r3, =crunch_owner
  189. add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area
  190. ldr r1, [r3] @ get current crunch owner
  191. teq r1, #0 @ any current owner?
  192. beq 1f @ no: quit
  193. teq r0, #0 @ any owner?
  194. teqne r1, r2 @ or specified one?
  195. bne 1f @ no: quit
  196. ldr r5, [r4, #0x80] @ enable access to crunch
  197. mov r2, #0xaa
  198. str r2, [r4, #0xc0]
  199. orr r5, r5, #0x00800000
  200. str r5, [r4, #0x80]
  201. mov r0, #0 @ nothing to load
  202. str r0, [r3] @ no more current owner
  203. ldr r2, [r4, #0x80] @ flush out enable (@@@)
  204. mov r2, r2
  205. bl crunch_save
  206. mov r2, #0xaa @ disable access to crunch
  207. str r2, [r4, #0xc0]
  208. bic r5, r5, #0x00800000
  209. str r5, [r4, #0x80]
  210. ldr r5, [r4, #0x80] @ flush out enable (@@@)
  211. mov r5, r5
  212. 1: msr cpsr_c, ip @ restore interrupt mode
  213. ldmfd sp!, {r4, r5, pc}
  214. /*
  215. * Copy crunch state to given memory address
  216. *
  217. * r0 = struct thread_info pointer of target task
  218. * r1 = memory address where to store crunch state
  219. *
  220. * this is called mainly in the creation of signal stack frames
  221. */
  222. ENTRY(crunch_task_copy)
  223. mrs ip, cpsr
  224. orr r2, ip, #PSR_I_BIT @ disable interrupts
  225. msr cpsr_c, r2
  226. ldr r3, =crunch_owner
  227. add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area
  228. ldr r3, [r3] @ get current crunch owner
  229. teq r2, r3 @ does this task own it...
  230. beq 1f
  231. @ current crunch values are in the task save area
  232. msr cpsr_c, ip @ restore interrupt mode
  233. mov r0, r1
  234. mov r1, r2
  235. mov r2, #CRUNCH_SIZE
  236. b memcpy
  237. 1: @ this task owns crunch regs -- grab a copy from there
  238. mov r0, #0 @ nothing to load
  239. mov r3, lr @ preserve return address
  240. bl crunch_save
  241. msr cpsr_c, ip @ restore interrupt mode
  242. mov pc, r3
  243. /*
  244. * Restore crunch state from given memory address
  245. *
  246. * r0 = struct thread_info pointer of target task
  247. * r1 = memory address where to get crunch state from
  248. *
  249. * this is used to restore crunch state when unwinding a signal stack frame
  250. */
  251. ENTRY(crunch_task_restore)
  252. mrs ip, cpsr
  253. orr r2, ip, #PSR_I_BIT @ disable interrupts
  254. msr cpsr_c, r2
  255. ldr r3, =crunch_owner
  256. add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area
  257. ldr r3, [r3] @ get current crunch owner
  258. teq r2, r3 @ does this task own it...
  259. beq 1f
  260. @ this task doesn't own crunch regs -- use its save area
  261. msr cpsr_c, ip @ restore interrupt mode
  262. mov r0, r2
  263. mov r2, #CRUNCH_SIZE
  264. b memcpy
  265. 1: @ this task owns crunch regs -- load them directly
  266. mov r0, r1
  267. mov r1, #0 @ nothing to save
  268. mov r3, lr @ preserve return address
  269. bl crunch_load
  270. msr cpsr_c, ip @ restore interrupt mode
  271. mov pc, r3