bios32.c 17 KB

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  1. /*
  2. * linux/arch/arm/kernel/bios32.c
  3. *
  4. * PCI bios-type initialisation for PCI machines
  5. *
  6. * Bits taken from various places.
  7. */
  8. #include <linux/module.h>
  9. #include <linux/kernel.h>
  10. #include <linux/pci.h>
  11. #include <linux/slab.h>
  12. #include <linux/init.h>
  13. #include <asm/io.h>
  14. #include <asm/mach-types.h>
  15. #include <asm/mach/pci.h>
  16. static int debug_pci;
  17. static int use_firmware;
  18. /*
  19. * We can't use pci_find_device() here since we are
  20. * called from interrupt context.
  21. */
  22. static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
  23. {
  24. struct pci_dev *dev;
  25. list_for_each_entry(dev, &bus->devices, bus_list) {
  26. u16 status;
  27. /*
  28. * ignore host bridge - we handle
  29. * that separately
  30. */
  31. if (dev->bus->number == 0 && dev->devfn == 0)
  32. continue;
  33. pci_read_config_word(dev, PCI_STATUS, &status);
  34. if (status == 0xffff)
  35. continue;
  36. if ((status & status_mask) == 0)
  37. continue;
  38. /* clear the status errors */
  39. pci_write_config_word(dev, PCI_STATUS, status & status_mask);
  40. if (warn)
  41. printk("(%s: %04X) ", pci_name(dev), status);
  42. }
  43. list_for_each_entry(dev, &bus->devices, bus_list)
  44. if (dev->subordinate)
  45. pcibios_bus_report_status(dev->subordinate, status_mask, warn);
  46. }
  47. void pcibios_report_status(u_int status_mask, int warn)
  48. {
  49. struct list_head *l;
  50. list_for_each(l, &pci_root_buses) {
  51. struct pci_bus *bus = pci_bus_b(l);
  52. pcibios_bus_report_status(bus, status_mask, warn);
  53. }
  54. }
  55. /*
  56. * We don't use this to fix the device, but initialisation of it.
  57. * It's not the correct use for this, but it works.
  58. * Note that the arbiter/ISA bridge appears to be buggy, specifically in
  59. * the following area:
  60. * 1. park on CPU
  61. * 2. ISA bridge ping-pong
  62. * 3. ISA bridge master handling of target RETRY
  63. *
  64. * Bug 3 is responsible for the sound DMA grinding to a halt. We now
  65. * live with bug 2.
  66. */
  67. static void __devinit pci_fixup_83c553(struct pci_dev *dev)
  68. {
  69. /*
  70. * Set memory region to start at address 0, and enable IO
  71. */
  72. pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
  73. pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
  74. dev->resource[0].end -= dev->resource[0].start;
  75. dev->resource[0].start = 0;
  76. /*
  77. * All memory requests from ISA to be channelled to PCI
  78. */
  79. pci_write_config_byte(dev, 0x48, 0xff);
  80. /*
  81. * Enable ping-pong on bus master to ISA bridge transactions.
  82. * This improves the sound DMA substantially. The fixed
  83. * priority arbiter also helps (see below).
  84. */
  85. pci_write_config_byte(dev, 0x42, 0x01);
  86. /*
  87. * Enable PCI retry
  88. */
  89. pci_write_config_byte(dev, 0x40, 0x22);
  90. /*
  91. * We used to set the arbiter to "park on last master" (bit
  92. * 1 set), but unfortunately the CyberPro does not park the
  93. * bus. We must therefore park on CPU. Unfortunately, this
  94. * may trigger yet another bug in the 553.
  95. */
  96. pci_write_config_byte(dev, 0x83, 0x02);
  97. /*
  98. * Make the ISA DMA request lowest priority, and disable
  99. * rotating priorities completely.
  100. */
  101. pci_write_config_byte(dev, 0x80, 0x11);
  102. pci_write_config_byte(dev, 0x81, 0x00);
  103. /*
  104. * Route INTA input to IRQ 11, and set IRQ11 to be level
  105. * sensitive.
  106. */
  107. pci_write_config_word(dev, 0x44, 0xb000);
  108. outb(0x08, 0x4d1);
  109. }
  110. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
  111. static void __devinit pci_fixup_unassign(struct pci_dev *dev)
  112. {
  113. dev->resource[0].end -= dev->resource[0].start;
  114. dev->resource[0].start = 0;
  115. }
  116. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
  117. /*
  118. * Prevent the PCI layer from seeing the resources allocated to this device
  119. * if it is the host bridge by marking it as such. These resources are of
  120. * no consequence to the PCI layer (they are handled elsewhere).
  121. */
  122. static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
  123. {
  124. int i;
  125. if (dev->devfn == 0) {
  126. dev->class &= 0xff;
  127. dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
  128. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  129. dev->resource[i].start = 0;
  130. dev->resource[i].end = 0;
  131. dev->resource[i].flags = 0;
  132. }
  133. }
  134. }
  135. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
  136. /*
  137. * Same as above. The PrPMC800 carrier board for the PrPMC1100
  138. * card maps the host-bridge @ 00:01:00 for some reason and it
  139. * ends up getting scanned. Note that we only want to do this
  140. * fixup when we find the IXP4xx on a PrPMC system, which is why
  141. * we check the machine type. We could be running on a board
  142. * with an IXP4xx target device and we don't want to kill the
  143. * resources in that case.
  144. */
  145. static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev)
  146. {
  147. int i;
  148. if (machine_is_prpmc1100()) {
  149. dev->class &= 0xff;
  150. dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
  151. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  152. dev->resource[i].start = 0;
  153. dev->resource[i].end = 0;
  154. dev->resource[i].flags = 0;
  155. }
  156. }
  157. }
  158. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP4XX, pci_fixup_prpmc1100);
  159. /*
  160. * PCI IDE controllers use non-standard I/O port decoding, respect it.
  161. */
  162. static void __devinit pci_fixup_ide_bases(struct pci_dev *dev)
  163. {
  164. struct resource *r;
  165. int i;
  166. if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
  167. return;
  168. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  169. r = dev->resource + i;
  170. if ((r->start & ~0x80) == 0x374) {
  171. r->start |= 2;
  172. r->end = r->start;
  173. }
  174. }
  175. }
  176. DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
  177. /*
  178. * Put the DEC21142 to sleep
  179. */
  180. static void __devinit pci_fixup_dec21142(struct pci_dev *dev)
  181. {
  182. pci_write_config_dword(dev, 0x40, 0x80000000);
  183. }
  184. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
  185. /*
  186. * The CY82C693 needs some rather major fixups to ensure that it does
  187. * the right thing. Idea from the Alpha people, with a few additions.
  188. *
  189. * We ensure that the IDE base registers are set to 1f0/3f4 for the
  190. * primary bus, and 170/374 for the secondary bus. Also, hide them
  191. * from the PCI subsystem view as well so we won't try to perform
  192. * our own auto-configuration on them.
  193. *
  194. * In addition, we ensure that the PCI IDE interrupts are routed to
  195. * IRQ 14 and IRQ 15 respectively.
  196. *
  197. * The above gets us to a point where the IDE on this device is
  198. * functional. However, The CY82C693U _does not work_ in bus
  199. * master mode without locking the PCI bus solid.
  200. */
  201. static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
  202. {
  203. if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
  204. u32 base0, base1;
  205. if (dev->class & 0x80) { /* primary */
  206. base0 = 0x1f0;
  207. base1 = 0x3f4;
  208. } else { /* secondary */
  209. base0 = 0x170;
  210. base1 = 0x374;
  211. }
  212. pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
  213. base0 | PCI_BASE_ADDRESS_SPACE_IO);
  214. pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
  215. base1 | PCI_BASE_ADDRESS_SPACE_IO);
  216. dev->resource[0].start = 0;
  217. dev->resource[0].end = 0;
  218. dev->resource[0].flags = 0;
  219. dev->resource[1].start = 0;
  220. dev->resource[1].end = 0;
  221. dev->resource[1].flags = 0;
  222. } else if (PCI_FUNC(dev->devfn) == 0) {
  223. /*
  224. * Setup IDE IRQ routing.
  225. */
  226. pci_write_config_byte(dev, 0x4b, 14);
  227. pci_write_config_byte(dev, 0x4c, 15);
  228. /*
  229. * Disable FREQACK handshake, enable USB.
  230. */
  231. pci_write_config_byte(dev, 0x4d, 0x41);
  232. /*
  233. * Enable PCI retry, and PCI post-write buffer.
  234. */
  235. pci_write_config_byte(dev, 0x44, 0x17);
  236. /*
  237. * Enable ISA master and DMA post write buffering.
  238. */
  239. pci_write_config_byte(dev, 0x45, 0x03);
  240. }
  241. }
  242. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
  243. void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
  244. {
  245. if (debug_pci)
  246. printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev));
  247. pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
  248. }
  249. /*
  250. * If the bus contains any of these devices, then we must not turn on
  251. * parity checking of any kind. Currently this is CyberPro 20x0 only.
  252. */
  253. static inline int pdev_bad_for_parity(struct pci_dev *dev)
  254. {
  255. return (dev->vendor == PCI_VENDOR_ID_INTERG &&
  256. (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
  257. dev->device == PCI_DEVICE_ID_INTERG_2010));
  258. }
  259. /*
  260. * Adjust the device resources from bus-centric to Linux-centric.
  261. */
  262. static void __devinit
  263. pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev)
  264. {
  265. resource_size_t offset;
  266. int i;
  267. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  268. if (dev->resource[i].start == 0)
  269. continue;
  270. if (dev->resource[i].flags & IORESOURCE_MEM)
  271. offset = root->mem_offset;
  272. else
  273. offset = root->io_offset;
  274. dev->resource[i].start += offset;
  275. dev->resource[i].end += offset;
  276. }
  277. }
  278. static void __devinit
  279. pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root)
  280. {
  281. struct pci_dev *dev = bus->self;
  282. int i;
  283. if (!dev) {
  284. /*
  285. * Assign root bus resources.
  286. */
  287. for (i = 0; i < 3; i++)
  288. bus->resource[i] = root->resource[i];
  289. }
  290. }
  291. /*
  292. * pcibios_fixup_bus - Called after each bus is probed,
  293. * but before its children are examined.
  294. */
  295. void __devinit pcibios_fixup_bus(struct pci_bus *bus)
  296. {
  297. struct pci_sys_data *root = bus->sysdata;
  298. struct pci_dev *dev;
  299. u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
  300. pbus_assign_bus_resources(bus, root);
  301. /*
  302. * Walk the devices on this bus, working out what we can
  303. * and can't support.
  304. */
  305. list_for_each_entry(dev, &bus->devices, bus_list) {
  306. u16 status;
  307. pdev_fixup_device_resources(root, dev);
  308. pci_read_config_word(dev, PCI_STATUS, &status);
  309. /*
  310. * If any device on this bus does not support fast back
  311. * to back transfers, then the bus as a whole is not able
  312. * to support them. Having fast back to back transfers
  313. * on saves us one PCI cycle per transaction.
  314. */
  315. if (!(status & PCI_STATUS_FAST_BACK))
  316. features &= ~PCI_COMMAND_FAST_BACK;
  317. if (pdev_bad_for_parity(dev))
  318. features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
  319. switch (dev->class >> 8) {
  320. case PCI_CLASS_BRIDGE_PCI:
  321. pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
  322. status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
  323. status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
  324. pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
  325. break;
  326. case PCI_CLASS_BRIDGE_CARDBUS:
  327. pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
  328. status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
  329. pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
  330. break;
  331. }
  332. }
  333. /*
  334. * Now walk the devices again, this time setting them up.
  335. */
  336. list_for_each_entry(dev, &bus->devices, bus_list) {
  337. u16 cmd;
  338. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  339. cmd |= features;
  340. pci_write_config_word(dev, PCI_COMMAND, cmd);
  341. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
  342. L1_CACHE_BYTES >> 2);
  343. }
  344. /*
  345. * Propagate the flags to the PCI bridge.
  346. */
  347. if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  348. if (features & PCI_COMMAND_FAST_BACK)
  349. bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
  350. if (features & PCI_COMMAND_PARITY)
  351. bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
  352. }
  353. /*
  354. * Report what we did for this bus
  355. */
  356. printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
  357. bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
  358. }
  359. /*
  360. * Convert from Linux-centric to bus-centric addresses for bridge devices.
  361. */
  362. void __devinit
  363. pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
  364. struct resource *res)
  365. {
  366. struct pci_sys_data *root = dev->sysdata;
  367. unsigned long offset = 0;
  368. if (res->flags & IORESOURCE_IO)
  369. offset = root->io_offset;
  370. if (res->flags & IORESOURCE_MEM)
  371. offset = root->mem_offset;
  372. region->start = res->start - offset;
  373. region->end = res->end - offset;
  374. }
  375. void __devinit
  376. pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
  377. struct pci_bus_region *region)
  378. {
  379. struct pci_sys_data *root = dev->sysdata;
  380. unsigned long offset = 0;
  381. if (res->flags & IORESOURCE_IO)
  382. offset = root->io_offset;
  383. if (res->flags & IORESOURCE_MEM)
  384. offset = root->mem_offset;
  385. res->start = region->start + offset;
  386. res->end = region->end + offset;
  387. }
  388. #ifdef CONFIG_HOTPLUG
  389. EXPORT_SYMBOL(pcibios_fixup_bus);
  390. EXPORT_SYMBOL(pcibios_resource_to_bus);
  391. EXPORT_SYMBOL(pcibios_bus_to_resource);
  392. #endif
  393. /*
  394. * This is the standard PCI-PCI bridge swizzling algorithm:
  395. *
  396. * Dev: 0 1 2 3
  397. * A A B C D
  398. * B B C D A
  399. * C C D A B
  400. * D D A B C
  401. * ^^^^^^^^^^ irq pin on bridge
  402. */
  403. u8 __devinit pci_std_swizzle(struct pci_dev *dev, u8 *pinp)
  404. {
  405. int pin = *pinp - 1;
  406. while (dev->bus->self) {
  407. pin = (pin + PCI_SLOT(dev->devfn)) & 3;
  408. /*
  409. * move up the chain of bridges,
  410. * swizzling as we go.
  411. */
  412. dev = dev->bus->self;
  413. }
  414. *pinp = pin + 1;
  415. return PCI_SLOT(dev->devfn);
  416. }
  417. /*
  418. * Swizzle the device pin each time we cross a bridge.
  419. * This might update pin and returns the slot number.
  420. */
  421. static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin)
  422. {
  423. struct pci_sys_data *sys = dev->sysdata;
  424. int slot = 0, oldpin = *pin;
  425. if (sys->swizzle)
  426. slot = sys->swizzle(dev, pin);
  427. if (debug_pci)
  428. printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
  429. pci_name(dev), oldpin, *pin, slot);
  430. return slot;
  431. }
  432. /*
  433. * Map a slot/pin to an IRQ.
  434. */
  435. static int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  436. {
  437. struct pci_sys_data *sys = dev->sysdata;
  438. int irq = -1;
  439. if (sys->map_irq)
  440. irq = sys->map_irq(dev, slot, pin);
  441. if (debug_pci)
  442. printk("PCI: %s mapping slot %d pin %d => irq %d\n",
  443. pci_name(dev), slot, pin, irq);
  444. return irq;
  445. }
  446. static void __init pcibios_init_hw(struct hw_pci *hw)
  447. {
  448. struct pci_sys_data *sys = NULL;
  449. int ret;
  450. int nr, busnr;
  451. for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
  452. sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
  453. if (!sys)
  454. panic("PCI: unable to allocate sys data!");
  455. sys->hw = hw;
  456. sys->busnr = busnr;
  457. sys->swizzle = hw->swizzle;
  458. sys->map_irq = hw->map_irq;
  459. sys->resource[0] = &ioport_resource;
  460. sys->resource[1] = &iomem_resource;
  461. ret = hw->setup(nr, sys);
  462. if (ret > 0) {
  463. sys->bus = hw->scan(nr, sys);
  464. if (!sys->bus)
  465. panic("PCI: unable to scan bus!");
  466. busnr = sys->bus->subordinate + 1;
  467. list_add(&sys->node, &hw->buses);
  468. } else {
  469. kfree(sys);
  470. if (ret < 0)
  471. break;
  472. }
  473. }
  474. }
  475. void __init pci_common_init(struct hw_pci *hw)
  476. {
  477. struct pci_sys_data *sys;
  478. INIT_LIST_HEAD(&hw->buses);
  479. if (hw->preinit)
  480. hw->preinit();
  481. pcibios_init_hw(hw);
  482. if (hw->postinit)
  483. hw->postinit();
  484. pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
  485. list_for_each_entry(sys, &hw->buses, node) {
  486. struct pci_bus *bus = sys->bus;
  487. if (!use_firmware) {
  488. /*
  489. * Size the bridge windows.
  490. */
  491. pci_bus_size_bridges(bus);
  492. /*
  493. * Assign resources.
  494. */
  495. pci_bus_assign_resources(bus);
  496. }
  497. /*
  498. * Tell drivers about devices found.
  499. */
  500. pci_bus_add_devices(bus);
  501. }
  502. }
  503. char * __init pcibios_setup(char *str)
  504. {
  505. if (!strcmp(str, "debug")) {
  506. debug_pci = 1;
  507. return NULL;
  508. } else if (!strcmp(str, "firmware")) {
  509. use_firmware = 1;
  510. return NULL;
  511. }
  512. return str;
  513. }
  514. /*
  515. * From arch/i386/kernel/pci-i386.c:
  516. *
  517. * We need to avoid collisions with `mirrored' VGA ports
  518. * and other strange ISA hardware, so we always want the
  519. * addresses to be allocated in the 0x000-0x0ff region
  520. * modulo 0x400.
  521. *
  522. * Why? Because some silly external IO cards only decode
  523. * the low 10 bits of the IO address. The 0x00-0xff region
  524. * is reserved for motherboard devices that decode all 16
  525. * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  526. * but we want to try to avoid allocating at 0x2900-0x2bff
  527. * which might be mirrored at 0x0100-0x03ff..
  528. */
  529. void pcibios_align_resource(void *data, struct resource *res,
  530. resource_size_t size, resource_size_t align)
  531. {
  532. resource_size_t start = res->start;
  533. if (res->flags & IORESOURCE_IO && start & 0x300)
  534. start = (start + 0x3ff) & ~0x3ff;
  535. res->start = (start + align - 1) & ~(align - 1);
  536. }
  537. /**
  538. * pcibios_enable_device - Enable I/O and memory.
  539. * @dev: PCI device to be enabled
  540. */
  541. int pcibios_enable_device(struct pci_dev *dev, int mask)
  542. {
  543. u16 cmd, old_cmd;
  544. int idx;
  545. struct resource *r;
  546. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  547. old_cmd = cmd;
  548. for (idx = 0; idx < 6; idx++) {
  549. /* Only set up the requested stuff */
  550. if (!(mask & (1 << idx)))
  551. continue;
  552. r = dev->resource + idx;
  553. if (!r->start && r->end) {
  554. printk(KERN_ERR "PCI: Device %s not available because"
  555. " of resource collisions\n", pci_name(dev));
  556. return -EINVAL;
  557. }
  558. if (r->flags & IORESOURCE_IO)
  559. cmd |= PCI_COMMAND_IO;
  560. if (r->flags & IORESOURCE_MEM)
  561. cmd |= PCI_COMMAND_MEMORY;
  562. }
  563. /*
  564. * Bridges (eg, cardbus bridges) need to be fully enabled
  565. */
  566. if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
  567. cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  568. if (cmd != old_cmd) {
  569. printk("PCI: enabling device %s (%04x -> %04x)\n",
  570. pci_name(dev), old_cmd, cmd);
  571. pci_write_config_word(dev, PCI_COMMAND, cmd);
  572. }
  573. return 0;
  574. }
  575. int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
  576. enum pci_mmap_state mmap_state, int write_combine)
  577. {
  578. struct pci_sys_data *root = dev->sysdata;
  579. unsigned long phys;
  580. if (mmap_state == pci_mmap_io) {
  581. return -EINVAL;
  582. } else {
  583. phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
  584. }
  585. /*
  586. * Mark this as IO
  587. */
  588. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  589. if (remap_pfn_range(vma, vma->vm_start, phys,
  590. vma->vm_end - vma->vm_start,
  591. vma->vm_page_prot))
  592. return -EAGAIN;
  593. return 0;
  594. }