vic.c 2.6 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798
  1. /*
  2. * linux/arch/arm/common/vic.c
  3. *
  4. * Copyright (C) 1999 - 2003 ARM Limited
  5. * Copyright (C) 2000 Deep Blue Solutions Ltd
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #include <linux/init.h>
  22. #include <linux/list.h>
  23. #include <asm/io.h>
  24. #include <asm/mach/irq.h>
  25. #include <asm/hardware/vic.h>
  26. static void vic_mask_irq(unsigned int irq)
  27. {
  28. void __iomem *base = get_irq_chip_data(irq);
  29. irq &= 31;
  30. writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
  31. }
  32. static void vic_unmask_irq(unsigned int irq)
  33. {
  34. void __iomem *base = get_irq_chip_data(irq);
  35. irq &= 31;
  36. writel(1 << irq, base + VIC_INT_ENABLE);
  37. }
  38. static struct irq_chip vic_chip = {
  39. .name = "VIC",
  40. .ack = vic_mask_irq,
  41. .mask = vic_mask_irq,
  42. .unmask = vic_unmask_irq,
  43. };
  44. /**
  45. * vic_init - initialise a vectored interrupt controller
  46. * @base: iomem base address
  47. * @irq_start: starting interrupt number, must be muliple of 32
  48. * @vic_sources: bitmask of interrupt sources to allow
  49. */
  50. void __init vic_init(void __iomem *base, unsigned int irq_start,
  51. u32 vic_sources)
  52. {
  53. unsigned int i;
  54. /* Disable all interrupts initially. */
  55. writel(0, base + VIC_INT_SELECT);
  56. writel(0, base + VIC_INT_ENABLE);
  57. writel(~0, base + VIC_INT_ENABLE_CLEAR);
  58. writel(0, base + VIC_IRQ_STATUS);
  59. writel(0, base + VIC_ITCR);
  60. writel(~0, base + VIC_INT_SOFT_CLEAR);
  61. /*
  62. * Make sure we clear all existing interrupts
  63. */
  64. writel(0, base + VIC_VECT_ADDR);
  65. for (i = 0; i < 19; i++) {
  66. unsigned int value;
  67. value = readl(base + VIC_VECT_ADDR);
  68. writel(value, base + VIC_VECT_ADDR);
  69. }
  70. for (i = 0; i < 16; i++) {
  71. void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
  72. writel(VIC_VECT_CNTL_ENABLE | i, reg);
  73. }
  74. writel(32, base + VIC_DEF_VECT_ADDR);
  75. for (i = 0; i < 32; i++) {
  76. unsigned int irq = irq_start + i;
  77. set_irq_chip(irq, &vic_chip);
  78. set_irq_chip_data(irq, base);
  79. if (vic_sources & (1 << i)) {
  80. set_irq_handler(irq, handle_level_irq);
  81. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  82. }
  83. }
  84. }