uengine.c 12 KB

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  1. /*
  2. * Generic library functions for the microengines found on the Intel
  3. * IXP2000 series of network processors.
  4. *
  5. * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
  6. * Dedicated to Marija Kulikova.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU Lesser General Public License as
  10. * published by the Free Software Foundation; either version 2.1 of the
  11. * License, or (at your option) any later version.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/slab.h>
  16. #include <linux/module.h>
  17. #include <linux/string.h>
  18. #include <asm/hardware.h>
  19. #include <asm/arch/hardware.h>
  20. #include <asm/hardware/uengine.h>
  21. #include <asm/io.h>
  22. #if defined(CONFIG_ARCH_IXP2000)
  23. #define IXP_UENGINE_CSR_VIRT_BASE IXP2000_UENGINE_CSR_VIRT_BASE
  24. #define IXP_PRODUCT_ID IXP2000_PRODUCT_ID
  25. #define IXP_MISC_CONTROL IXP2000_MISC_CONTROL
  26. #define IXP_RESET1 IXP2000_RESET1
  27. #else
  28. #if defined(CONFIG_ARCH_IXP23XX)
  29. #define IXP_UENGINE_CSR_VIRT_BASE IXP23XX_UENGINE_CSR_VIRT_BASE
  30. #define IXP_PRODUCT_ID IXP23XX_PRODUCT_ID
  31. #define IXP_MISC_CONTROL IXP23XX_MISC_CONTROL
  32. #define IXP_RESET1 IXP23XX_RESET1
  33. #else
  34. #error unknown platform
  35. #endif
  36. #endif
  37. #define USTORE_ADDRESS 0x000
  38. #define USTORE_DATA_LOWER 0x004
  39. #define USTORE_DATA_UPPER 0x008
  40. #define CTX_ENABLES 0x018
  41. #define CC_ENABLE 0x01c
  42. #define CSR_CTX_POINTER 0x020
  43. #define INDIRECT_CTX_STS 0x040
  44. #define ACTIVE_CTX_STS 0x044
  45. #define INDIRECT_CTX_SIG_EVENTS 0x048
  46. #define INDIRECT_CTX_WAKEUP_EVENTS 0x050
  47. #define NN_PUT 0x080
  48. #define NN_GET 0x084
  49. #define TIMESTAMP_LOW 0x0c0
  50. #define TIMESTAMP_HIGH 0x0c4
  51. #define T_INDEX_BYTE_INDEX 0x0f4
  52. #define LOCAL_CSR_STATUS 0x180
  53. u32 ixp2000_uengine_mask;
  54. static void *ixp2000_uengine_csr_area(int uengine)
  55. {
  56. return ((void *)IXP_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
  57. }
  58. /*
  59. * LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR
  60. * space means that the microengine we tried to access was also trying
  61. * to access its own CSR space on the same clock cycle as we did. When
  62. * this happens, we lose the arbitration process by default, and the
  63. * read or write we tried to do was not actually performed, so we try
  64. * again until it succeeds.
  65. */
  66. u32 ixp2000_uengine_csr_read(int uengine, int offset)
  67. {
  68. void *uebase;
  69. u32 *local_csr_status;
  70. u32 *reg;
  71. u32 value;
  72. uebase = ixp2000_uengine_csr_area(uengine);
  73. local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
  74. reg = (u32 *)(uebase + offset);
  75. do {
  76. value = ixp2000_reg_read(reg);
  77. } while (ixp2000_reg_read(local_csr_status) & 1);
  78. return value;
  79. }
  80. EXPORT_SYMBOL(ixp2000_uengine_csr_read);
  81. void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
  82. {
  83. void *uebase;
  84. u32 *local_csr_status;
  85. u32 *reg;
  86. uebase = ixp2000_uengine_csr_area(uengine);
  87. local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
  88. reg = (u32 *)(uebase + offset);
  89. do {
  90. ixp2000_reg_write(reg, value);
  91. } while (ixp2000_reg_read(local_csr_status) & 1);
  92. }
  93. EXPORT_SYMBOL(ixp2000_uengine_csr_write);
  94. void ixp2000_uengine_reset(u32 uengine_mask)
  95. {
  96. u32 value;
  97. value = ixp2000_reg_read(IXP_RESET1) & ~ixp2000_uengine_mask;
  98. uengine_mask &= ixp2000_uengine_mask;
  99. ixp2000_reg_wrb(IXP_RESET1, value | uengine_mask);
  100. ixp2000_reg_wrb(IXP_RESET1, value);
  101. }
  102. EXPORT_SYMBOL(ixp2000_uengine_reset);
  103. void ixp2000_uengine_set_mode(int uengine, u32 mode)
  104. {
  105. /*
  106. * CTL_STR_PAR_EN: unconditionally enable parity checking on
  107. * control store.
  108. */
  109. mode |= 0x10000000;
  110. ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);
  111. /*
  112. * Enable updating of condition codes.
  113. */
  114. ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);
  115. /*
  116. * Initialise other per-microengine registers.
  117. */
  118. ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
  119. ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
  120. ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
  121. }
  122. EXPORT_SYMBOL(ixp2000_uengine_set_mode);
  123. static int make_even_parity(u32 x)
  124. {
  125. return hweight32(x) & 1;
  126. }
  127. static void ustore_write(int uengine, u64 insn)
  128. {
  129. /*
  130. * Generate even parity for top and bottom 20 bits.
  131. */
  132. insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41;
  133. insn |= (u64)make_even_parity(insn & 0x000fffff) << 40;
  134. /*
  135. * Write to microstore. The second write auto-increments
  136. * the USTORE_ADDRESS index register.
  137. */
  138. ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
  139. ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
  140. }
  141. void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
  142. {
  143. int i;
  144. /*
  145. * Start writing to microstore at address 0.
  146. */
  147. ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
  148. for (i = 0; i < insns; i++) {
  149. u64 insn;
  150. insn = (((u64)ucode[0]) << 32) |
  151. (((u64)ucode[1]) << 24) |
  152. (((u64)ucode[2]) << 16) |
  153. (((u64)ucode[3]) << 8) |
  154. ((u64)ucode[4]);
  155. ucode += 5;
  156. ustore_write(uengine, insn);
  157. }
  158. /*
  159. * Pad with a few NOPs at the end (to avoid the microengine
  160. * aborting as it prefetches beyond the last instruction), unless
  161. * we run off the end of the instruction store first, at which
  162. * point the address register will wrap back to zero.
  163. */
  164. for (i = 0; i < 4; i++) {
  165. u32 addr;
  166. addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
  167. if (addr == 0x80000000)
  168. break;
  169. ustore_write(uengine, 0xf0000c0300ULL);
  170. }
  171. /*
  172. * End programming.
  173. */
  174. ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
  175. }
  176. EXPORT_SYMBOL(ixp2000_uengine_load_microcode);
  177. void ixp2000_uengine_init_context(int uengine, int context, int pc)
  178. {
  179. /*
  180. * Select the right context for indirect access.
  181. */
  182. ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);
  183. /*
  184. * Initialise signal masks to immediately go to Ready state.
  185. */
  186. ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
  187. ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);
  188. /*
  189. * Set program counter.
  190. */
  191. ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
  192. }
  193. EXPORT_SYMBOL(ixp2000_uengine_init_context);
  194. void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
  195. {
  196. u32 mask;
  197. /*
  198. * Enable the specified context to go to Executing state.
  199. */
  200. mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
  201. mask |= ctx_mask << 8;
  202. ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
  203. }
  204. EXPORT_SYMBOL(ixp2000_uengine_start_contexts);
  205. void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
  206. {
  207. u32 mask;
  208. /*
  209. * Disable the Ready->Executing transition. Note that this
  210. * does not stop the context until it voluntarily yields.
  211. */
  212. mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
  213. mask &= ~(ctx_mask << 8);
  214. ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
  215. }
  216. EXPORT_SYMBOL(ixp2000_uengine_stop_contexts);
  217. static int check_ixp_type(struct ixp2000_uengine_code *c)
  218. {
  219. u32 product_id;
  220. u32 rev;
  221. product_id = ixp2000_reg_read(IXP_PRODUCT_ID);
  222. if (((product_id >> 16) & 0x1f) != 0)
  223. return 0;
  224. switch ((product_id >> 8) & 0xff) {
  225. #ifdef CONFIG_ARCH_IXP2000
  226. case 0: /* IXP2800 */
  227. if (!(c->cpu_model_bitmask & 4))
  228. return 0;
  229. break;
  230. case 1: /* IXP2850 */
  231. if (!(c->cpu_model_bitmask & 8))
  232. return 0;
  233. break;
  234. case 2: /* IXP2400 */
  235. if (!(c->cpu_model_bitmask & 2))
  236. return 0;
  237. break;
  238. #endif
  239. #ifdef CONFIG_ARCH_IXP23XX
  240. case 4: /* IXP23xx */
  241. if (!(c->cpu_model_bitmask & 0x3f0))
  242. return 0;
  243. break;
  244. #endif
  245. default:
  246. return 0;
  247. }
  248. rev = product_id & 0xff;
  249. if (rev < c->cpu_min_revision || rev > c->cpu_max_revision)
  250. return 0;
  251. return 1;
  252. }
  253. static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
  254. {
  255. int offset;
  256. int i;
  257. offset = 0;
  258. for (i = 0; i < 128; i++) {
  259. u8 b3;
  260. u8 b2;
  261. u8 b1;
  262. u8 b0;
  263. b3 = (gpr_a[i] >> 24) & 0xff;
  264. b2 = (gpr_a[i] >> 16) & 0xff;
  265. b1 = (gpr_a[i] >> 8) & 0xff;
  266. b0 = gpr_a[i] & 0xff;
  267. // immed[@ai, (b1 << 8) | b0]
  268. // 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII
  269. ucode[offset++] = 0xf0;
  270. ucode[offset++] = (b1 >> 4);
  271. ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6);
  272. ucode[offset++] = (b0 << 2);
  273. ucode[offset++] = 0x80 | i;
  274. // immed_w1[@ai, (b3 << 8) | b2]
  275. // 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII
  276. ucode[offset++] = 0xf4;
  277. ucode[offset++] = 0x40 | (b3 >> 4);
  278. ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6);
  279. ucode[offset++] = (b2 << 2);
  280. ucode[offset++] = 0x80 | i;
  281. }
  282. for (i = 0; i < 128; i++) {
  283. u8 b3;
  284. u8 b2;
  285. u8 b1;
  286. u8 b0;
  287. b3 = (gpr_b[i] >> 24) & 0xff;
  288. b2 = (gpr_b[i] >> 16) & 0xff;
  289. b1 = (gpr_b[i] >> 8) & 0xff;
  290. b0 = gpr_b[i] & 0xff;
  291. // immed[@bi, (b1 << 8) | b0]
  292. // 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV
  293. ucode[offset++] = 0xf0;
  294. ucode[offset++] = (b1 >> 4);
  295. ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6);
  296. ucode[offset++] = (i << 2) | 0x03;
  297. ucode[offset++] = b0;
  298. // immed_w1[@bi, (b3 << 8) | b2]
  299. // 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV
  300. ucode[offset++] = 0xf4;
  301. ucode[offset++] = 0x40 | (b3 >> 4);
  302. ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6);
  303. ucode[offset++] = (i << 2) | 0x03;
  304. ucode[offset++] = b2;
  305. }
  306. // ctx_arb[kill]
  307. ucode[offset++] = 0xe0;
  308. ucode[offset++] = 0x00;
  309. ucode[offset++] = 0x01;
  310. ucode[offset++] = 0x00;
  311. ucode[offset++] = 0x00;
  312. }
  313. static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
  314. {
  315. int per_ctx_regs;
  316. u32 *gpr_a;
  317. u32 *gpr_b;
  318. u8 *ucode;
  319. int i;
  320. gpr_a = kmalloc(128 * sizeof(u32), GFP_KERNEL);
  321. gpr_b = kmalloc(128 * sizeof(u32), GFP_KERNEL);
  322. ucode = kmalloc(513 * 5, GFP_KERNEL);
  323. if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) {
  324. kfree(ucode);
  325. kfree(gpr_b);
  326. kfree(gpr_a);
  327. return 1;
  328. }
  329. per_ctx_regs = 16;
  330. if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS)
  331. per_ctx_regs = 32;
  332. memset(gpr_a, 0, sizeof(gpr_a));
  333. memset(gpr_b, 0, sizeof(gpr_b));
  334. for (i = 0; i < 256; i++) {
  335. struct ixp2000_reg_value *r = c->initial_reg_values + i;
  336. u32 *bank;
  337. int inc;
  338. int j;
  339. if (r->reg == -1)
  340. break;
  341. bank = (r->reg & 0x400) ? gpr_b : gpr_a;
  342. inc = (r->reg & 0x80) ? 128 : per_ctx_regs;
  343. j = r->reg & 0x7f;
  344. while (j < 128) {
  345. bank[j] = r->value;
  346. j += inc;
  347. }
  348. }
  349. generate_ucode(ucode, gpr_a, gpr_b);
  350. ixp2000_uengine_load_microcode(uengine, ucode, 513);
  351. ixp2000_uengine_init_context(uengine, 0, 0);
  352. ixp2000_uengine_start_contexts(uengine, 0x01);
  353. for (i = 0; i < 100; i++) {
  354. u32 status;
  355. status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
  356. if (!(status & 0x80000000))
  357. break;
  358. }
  359. ixp2000_uengine_stop_contexts(uengine, 0x01);
  360. kfree(ucode);
  361. kfree(gpr_b);
  362. kfree(gpr_a);
  363. return !!(i == 100);
  364. }
  365. int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
  366. {
  367. int ctx;
  368. if (!check_ixp_type(c))
  369. return 1;
  370. if (!(ixp2000_uengine_mask & (1 << uengine)))
  371. return 1;
  372. ixp2000_uengine_reset(1 << uengine);
  373. ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
  374. if (set_initial_registers(uengine, c))
  375. return 1;
  376. ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);
  377. for (ctx = 0; ctx < 8; ctx++)
  378. ixp2000_uengine_init_context(uengine, ctx, 0);
  379. return 0;
  380. }
  381. EXPORT_SYMBOL(ixp2000_uengine_load);
  382. static int __init ixp2000_uengine_init(void)
  383. {
  384. int uengine;
  385. u32 value;
  386. /*
  387. * Determine number of microengines present.
  388. */
  389. switch ((ixp2000_reg_read(IXP_PRODUCT_ID) >> 8) & 0x1fff) {
  390. #ifdef CONFIG_ARCH_IXP2000
  391. case 0: /* IXP2800 */
  392. case 1: /* IXP2850 */
  393. ixp2000_uengine_mask = 0x00ff00ff;
  394. break;
  395. case 2: /* IXP2400 */
  396. ixp2000_uengine_mask = 0x000f000f;
  397. break;
  398. #endif
  399. #ifdef CONFIG_ARCH_IXP23XX
  400. case 4: /* IXP23xx */
  401. ixp2000_uengine_mask = (*IXP23XX_EXP_CFG_FUSE >> 8) & 0xf;
  402. break;
  403. #endif
  404. default:
  405. printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n",
  406. (unsigned int)ixp2000_reg_read(IXP_PRODUCT_ID));
  407. ixp2000_uengine_mask = 0x00000000;
  408. break;
  409. }
  410. /*
  411. * Reset microengines.
  412. */
  413. ixp2000_uengine_reset(ixp2000_uengine_mask);
  414. /*
  415. * Synchronise timestamp counters across all microengines.
  416. */
  417. value = ixp2000_reg_read(IXP_MISC_CONTROL);
  418. ixp2000_reg_wrb(IXP_MISC_CONTROL, value & ~0x80);
  419. for (uengine = 0; uengine < 32; uengine++) {
  420. if (ixp2000_uengine_mask & (1 << uengine)) {
  421. ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
  422. ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
  423. }
  424. }
  425. ixp2000_reg_wrb(IXP_MISC_CONTROL, value | 0x80);
  426. return 0;
  427. }
  428. subsys_initcall(ixp2000_uengine_init);