icst525.c 3.3 KB

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  1. /*
  2. * linux/arch/arm/common/icst525.c
  3. *
  4. * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Support functions for calculating clocks/divisors for the ICST525
  11. * clock generators. See http://www.icst.com/ for more information
  12. * on these devices.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <asm/hardware/icst525.h>
  17. /*
  18. * Divisors for each OD setting.
  19. */
  20. static unsigned char s2div[8] = { 10, 2, 8, 4, 5, 7, 9, 6 };
  21. unsigned long icst525_khz(const struct icst525_params *p, struct icst525_vco vco)
  22. {
  23. return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * s2div[vco.s]);
  24. }
  25. EXPORT_SYMBOL(icst525_khz);
  26. /*
  27. * Ascending divisor S values.
  28. */
  29. static unsigned char idx2s[] = { 1, 3, 4, 7, 5, 2, 6, 0 };
  30. struct icst525_vco
  31. icst525_khz_to_vco(const struct icst525_params *p, unsigned long freq)
  32. {
  33. struct icst525_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
  34. unsigned long f;
  35. unsigned int i = 0, rd, best = (unsigned int)-1;
  36. /*
  37. * First, find the PLL output divisor such
  38. * that the PLL output is within spec.
  39. */
  40. do {
  41. f = freq * s2div[idx2s[i]];
  42. /*
  43. * f must be between 10MHz and
  44. * 320MHz (5V) or 200MHz (3V)
  45. */
  46. if (f > 10000 && f <= p->vco_max)
  47. break;
  48. } while (i < ARRAY_SIZE(idx2s));
  49. if (i >= ARRAY_SIZE(idx2s))
  50. return vco;
  51. vco.s = idx2s[i];
  52. /*
  53. * Now find the closest divisor combination
  54. * which gives a PLL output of 'f'.
  55. */
  56. for (rd = p->rd_min; rd <= p->rd_max; rd++) {
  57. unsigned long fref_div, f_pll;
  58. unsigned int vd;
  59. int f_diff;
  60. fref_div = (2 * p->ref) / rd;
  61. vd = (f + fref_div / 2) / fref_div;
  62. if (vd < p->vd_min || vd > p->vd_max)
  63. continue;
  64. f_pll = fref_div * vd;
  65. f_diff = f_pll - f;
  66. if (f_diff < 0)
  67. f_diff = -f_diff;
  68. if ((unsigned)f_diff < best) {
  69. vco.v = vd - 8;
  70. vco.r = rd - 2;
  71. if (f_diff == 0)
  72. break;
  73. best = f_diff;
  74. }
  75. }
  76. return vco;
  77. }
  78. EXPORT_SYMBOL(icst525_khz_to_vco);
  79. struct icst525_vco
  80. icst525_ps_to_vco(const struct icst525_params *p, unsigned long period)
  81. {
  82. struct icst525_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
  83. unsigned long f, ps;
  84. unsigned int i = 0, rd, best = (unsigned int)-1;
  85. ps = 1000000000UL / p->vco_max;
  86. /*
  87. * First, find the PLL output divisor such
  88. * that the PLL output is within spec.
  89. */
  90. do {
  91. f = period / s2div[idx2s[i]];
  92. /*
  93. * f must be between 10MHz and
  94. * 320MHz (5V) or 200MHz (3V)
  95. */
  96. if (f >= ps && f < 100000)
  97. break;
  98. } while (i < ARRAY_SIZE(idx2s));
  99. if (i >= ARRAY_SIZE(idx2s))
  100. return vco;
  101. vco.s = idx2s[i];
  102. ps = 500000000UL / p->ref;
  103. /*
  104. * Now find the closest divisor combination
  105. * which gives a PLL output of 'f'.
  106. */
  107. for (rd = p->rd_min; rd <= p->rd_max; rd++) {
  108. unsigned long f_in_div, f_pll;
  109. unsigned int vd;
  110. int f_diff;
  111. f_in_div = ps * rd;
  112. vd = (f_in_div + f / 2) / f;
  113. if (vd < p->vd_min || vd > p->vd_max)
  114. continue;
  115. f_pll = (f_in_div + vd / 2) / vd;
  116. f_diff = f_pll - f;
  117. if (f_diff < 0)
  118. f_diff = -f_diff;
  119. if ((unsigned)f_diff < best) {
  120. vco.v = vd - 8;
  121. vco.r = rd - 2;
  122. if (f_diff == 0)
  123. break;
  124. best = f_diff;
  125. }
  126. }
  127. return vco;
  128. }
  129. EXPORT_SYMBOL(icst525_ps_to_vco);