icst307.c 3.4 KB

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  1. /*
  2. * linux/arch/arm/common/icst307.c
  3. *
  4. * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Support functions for calculating clocks/divisors for the ICST307
  11. * clock generators. See http://www.icst.com/ for more information
  12. * on these devices.
  13. *
  14. * This is an almost identical implementation to the ICST525 clock generator.
  15. * The s2div and idx2s files are different
  16. */
  17. #include <linux/module.h>
  18. #include <linux/kernel.h>
  19. #include <asm/hardware/icst307.h>
  20. /*
  21. * Divisors for each OD setting.
  22. */
  23. static unsigned char s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 };
  24. unsigned long icst307_khz(const struct icst307_params *p, struct icst307_vco vco)
  25. {
  26. return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * s2div[vco.s]);
  27. }
  28. EXPORT_SYMBOL(icst307_khz);
  29. /*
  30. * Ascending divisor S values.
  31. */
  32. static unsigned char idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 };
  33. struct icst307_vco
  34. icst307_khz_to_vco(const struct icst307_params *p, unsigned long freq)
  35. {
  36. struct icst307_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
  37. unsigned long f;
  38. unsigned int i = 0, rd, best = (unsigned int)-1;
  39. /*
  40. * First, find the PLL output divisor such
  41. * that the PLL output is within spec.
  42. */
  43. do {
  44. f = freq * s2div[idx2s[i]];
  45. /*
  46. * f must be between 6MHz and 200MHz (3.3 or 5V)
  47. */
  48. if (f > 6000 && f <= p->vco_max)
  49. break;
  50. } while (i < ARRAY_SIZE(idx2s));
  51. if (i >= ARRAY_SIZE(idx2s))
  52. return vco;
  53. vco.s = idx2s[i];
  54. /*
  55. * Now find the closest divisor combination
  56. * which gives a PLL output of 'f'.
  57. */
  58. for (rd = p->rd_min; rd <= p->rd_max; rd++) {
  59. unsigned long fref_div, f_pll;
  60. unsigned int vd;
  61. int f_diff;
  62. fref_div = (2 * p->ref) / rd;
  63. vd = (f + fref_div / 2) / fref_div;
  64. if (vd < p->vd_min || vd > p->vd_max)
  65. continue;
  66. f_pll = fref_div * vd;
  67. f_diff = f_pll - f;
  68. if (f_diff < 0)
  69. f_diff = -f_diff;
  70. if ((unsigned)f_diff < best) {
  71. vco.v = vd - 8;
  72. vco.r = rd - 2;
  73. if (f_diff == 0)
  74. break;
  75. best = f_diff;
  76. }
  77. }
  78. return vco;
  79. }
  80. EXPORT_SYMBOL(icst307_khz_to_vco);
  81. struct icst307_vco
  82. icst307_ps_to_vco(const struct icst307_params *p, unsigned long period)
  83. {
  84. struct icst307_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
  85. unsigned long f, ps;
  86. unsigned int i = 0, rd, best = (unsigned int)-1;
  87. ps = 1000000000UL / p->vco_max;
  88. /*
  89. * First, find the PLL output divisor such
  90. * that the PLL output is within spec.
  91. */
  92. do {
  93. f = period / s2div[idx2s[i]];
  94. /*
  95. * f must be between 6MHz and 200MHz (3.3 or 5V)
  96. */
  97. if (f >= ps && f < 1000000000UL / 6000 + 1)
  98. break;
  99. } while (i < ARRAY_SIZE(idx2s));
  100. if (i >= ARRAY_SIZE(idx2s))
  101. return vco;
  102. vco.s = idx2s[i];
  103. ps = 500000000UL / p->ref;
  104. /*
  105. * Now find the closest divisor combination
  106. * which gives a PLL output of 'f'.
  107. */
  108. for (rd = p->rd_min; rd <= p->rd_max; rd++) {
  109. unsigned long f_in_div, f_pll;
  110. unsigned int vd;
  111. int f_diff;
  112. f_in_div = ps * rd;
  113. vd = (f_in_div + f / 2) / f;
  114. if (vd < p->vd_min || vd > p->vd_max)
  115. continue;
  116. f_pll = (f_in_div + vd / 2) / vd;
  117. f_diff = f_pll - f;
  118. if (f_diff < 0)
  119. f_diff = -f_diff;
  120. if ((unsigned)f_diff < best) {
  121. vco.v = vd - 8;
  122. vco.r = rd - 2;
  123. if (f_diff == 0)
  124. break;
  125. best = f_diff;
  126. }
  127. }
  128. return vco;
  129. }
  130. EXPORT_SYMBOL(icst307_ps_to_vco);