gic.c 6.7 KB

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  1. /*
  2. * linux/arch/arm/common/gic.c
  3. *
  4. * Copyright (C) 2002 ARM Limited, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Interrupt architecture for the GIC:
  11. *
  12. * o There is one Interrupt Distributor, which receives interrupts
  13. * from system devices and sends them to the Interrupt Controllers.
  14. *
  15. * o There is one CPU Interface per CPU, which sends interrupts sent
  16. * by the Distributor, and interrupts generated locally, to the
  17. * associated CPU. The base address of the CPU interface is usually
  18. * aliased so that the same address points to different chips depending
  19. * on the CPU it is accessed from.
  20. *
  21. * Note that IRQs 0-31 are special - they are local to each CPU.
  22. * As such, the enable set/clear, pending set/clear and active bit
  23. * registers are banked per-cpu for these sources.
  24. */
  25. #include <linux/init.h>
  26. #include <linux/kernel.h>
  27. #include <linux/list.h>
  28. #include <linux/smp.h>
  29. #include <linux/cpumask.h>
  30. #include <asm/irq.h>
  31. #include <asm/io.h>
  32. #include <asm/mach/irq.h>
  33. #include <asm/hardware/gic.h>
  34. static DEFINE_SPINLOCK(irq_controller_lock);
  35. struct gic_chip_data {
  36. unsigned int irq_offset;
  37. void __iomem *dist_base;
  38. void __iomem *cpu_base;
  39. };
  40. #ifndef MAX_GIC_NR
  41. #define MAX_GIC_NR 1
  42. #endif
  43. static struct gic_chip_data gic_data[MAX_GIC_NR];
  44. static inline void __iomem *gic_dist_base(unsigned int irq)
  45. {
  46. struct gic_chip_data *gic_data = get_irq_chip_data(irq);
  47. return gic_data->dist_base;
  48. }
  49. static inline void __iomem *gic_cpu_base(unsigned int irq)
  50. {
  51. struct gic_chip_data *gic_data = get_irq_chip_data(irq);
  52. return gic_data->cpu_base;
  53. }
  54. static inline unsigned int gic_irq(unsigned int irq)
  55. {
  56. struct gic_chip_data *gic_data = get_irq_chip_data(irq);
  57. return irq - gic_data->irq_offset;
  58. }
  59. /*
  60. * Routines to acknowledge, disable and enable interrupts
  61. *
  62. * Linux assumes that when we're done with an interrupt we need to
  63. * unmask it, in the same way we need to unmask an interrupt when
  64. * we first enable it.
  65. *
  66. * The GIC has a seperate notion of "end of interrupt" to re-enable
  67. * an interrupt after handling, in order to support hardware
  68. * prioritisation.
  69. *
  70. * We can make the GIC behave in the way that Linux expects by making
  71. * our "acknowledge" routine disable the interrupt, then mark it as
  72. * complete.
  73. */
  74. static void gic_ack_irq(unsigned int irq)
  75. {
  76. u32 mask = 1 << (irq % 32);
  77. spin_lock(&irq_controller_lock);
  78. writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
  79. writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
  80. spin_unlock(&irq_controller_lock);
  81. }
  82. static void gic_mask_irq(unsigned int irq)
  83. {
  84. u32 mask = 1 << (irq % 32);
  85. spin_lock(&irq_controller_lock);
  86. writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
  87. spin_unlock(&irq_controller_lock);
  88. }
  89. static void gic_unmask_irq(unsigned int irq)
  90. {
  91. u32 mask = 1 << (irq % 32);
  92. spin_lock(&irq_controller_lock);
  93. writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4);
  94. spin_unlock(&irq_controller_lock);
  95. }
  96. #ifdef CONFIG_SMP
  97. static void gic_set_cpu(unsigned int irq, cpumask_t mask_val)
  98. {
  99. void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3);
  100. unsigned int shift = (irq % 4) * 8;
  101. unsigned int cpu = first_cpu(mask_val);
  102. u32 val;
  103. spin_lock(&irq_controller_lock);
  104. irq_desc[irq].cpu = cpu;
  105. val = readl(reg) & ~(0xff << shift);
  106. val |= 1 << (cpu + shift);
  107. writel(val, reg);
  108. spin_unlock(&irq_controller_lock);
  109. }
  110. #endif
  111. static void fastcall gic_handle_cascade_irq(unsigned int irq,
  112. struct irq_desc *desc)
  113. {
  114. struct gic_chip_data *chip_data = get_irq_data(irq);
  115. struct irq_chip *chip = get_irq_chip(irq);
  116. unsigned int cascade_irq;
  117. unsigned long status;
  118. /* primary controller ack'ing */
  119. chip->ack(irq);
  120. spin_lock(&irq_controller_lock);
  121. status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
  122. spin_unlock(&irq_controller_lock);
  123. cascade_irq = (status & 0x3ff);
  124. if (cascade_irq > 1020)
  125. goto out;
  126. if (cascade_irq < 32 || cascade_irq >= NR_IRQS) {
  127. do_bad_IRQ(cascade_irq, desc);
  128. goto out;
  129. }
  130. cascade_irq += chip_data->irq_offset;
  131. generic_handle_irq(cascade_irq);
  132. out:
  133. /* primary controller unmasking */
  134. chip->unmask(irq);
  135. }
  136. static struct irq_chip gic_chip = {
  137. .name = "GIC",
  138. .ack = gic_ack_irq,
  139. .mask = gic_mask_irq,
  140. .unmask = gic_unmask_irq,
  141. #ifdef CONFIG_SMP
  142. .set_affinity = gic_set_cpu,
  143. #endif
  144. };
  145. void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
  146. {
  147. if (gic_nr >= MAX_GIC_NR)
  148. BUG();
  149. if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
  150. BUG();
  151. set_irq_chained_handler(irq, gic_handle_cascade_irq);
  152. }
  153. void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
  154. unsigned int irq_start)
  155. {
  156. unsigned int max_irq, i;
  157. u32 cpumask = 1 << smp_processor_id();
  158. if (gic_nr >= MAX_GIC_NR)
  159. BUG();
  160. cpumask |= cpumask << 8;
  161. cpumask |= cpumask << 16;
  162. gic_data[gic_nr].dist_base = base;
  163. gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;
  164. writel(0, base + GIC_DIST_CTRL);
  165. /*
  166. * Find out how many interrupts are supported.
  167. */
  168. max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
  169. max_irq = (max_irq + 1) * 32;
  170. /*
  171. * The GIC only supports up to 1020 interrupt sources.
  172. * Limit this to either the architected maximum, or the
  173. * platform maximum.
  174. */
  175. if (max_irq > max(1020, NR_IRQS))
  176. max_irq = max(1020, NR_IRQS);
  177. /*
  178. * Set all global interrupts to be level triggered, active low.
  179. */
  180. for (i = 32; i < max_irq; i += 16)
  181. writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
  182. /*
  183. * Set all global interrupts to this CPU only.
  184. */
  185. for (i = 32; i < max_irq; i += 4)
  186. writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
  187. /*
  188. * Set priority on all interrupts.
  189. */
  190. for (i = 0; i < max_irq; i += 4)
  191. writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
  192. /*
  193. * Disable all interrupts.
  194. */
  195. for (i = 0; i < max_irq; i += 32)
  196. writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
  197. /*
  198. * Setup the Linux IRQ subsystem.
  199. */
  200. for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
  201. set_irq_chip(i, &gic_chip);
  202. set_irq_chip_data(i, &gic_data[gic_nr]);
  203. set_irq_handler(i, handle_level_irq);
  204. set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
  205. }
  206. writel(1, base + GIC_DIST_CTRL);
  207. }
  208. void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
  209. {
  210. if (gic_nr >= MAX_GIC_NR)
  211. BUG();
  212. gic_data[gic_nr].cpu_base = base;
  213. writel(0xf0, base + GIC_CPU_PRIMASK);
  214. writel(1, base + GIC_CPU_CTRL);
  215. }
  216. #ifdef CONFIG_SMP
  217. void gic_raise_softirq(cpumask_t cpumask, unsigned int irq)
  218. {
  219. unsigned long map = *cpus_addr(cpumask);
  220. /* this always happens on GIC0 */
  221. writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
  222. }
  223. #endif