voyager.txt 3.4 KB

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  1. Running Linux on the Voyager Architecture
  2. =========================================
  3. For full details and current project status, see
  4. http://www.hansenpartnership.com/voyager
  5. The voyager architecture was designed by NCR in the mid 80s to be a
  6. fully SMP capable RAS computing architecture built around intel's 486
  7. chip set. The voyager came in three levels of architectural
  8. sophistication: 3,4 and 5 --- 1 and 2 never made it out of prototype.
  9. The linux patches support only the Level 5 voyager architecture (any
  10. machine class 3435 and above).
  11. The Voyager Architecture
  12. ------------------------
  13. Voyager machines consist of a Baseboard with a 386 diagnostic
  14. processor, a Power Supply Interface (PSI) a Primary and possibly
  15. Secondary Microchannel bus and between 2 and 20 voyager slots. The
  16. voyager slots can be populated with memory and cpu cards (up to 4GB
  17. memory and from 1 486 to 32 Pentium Pro processors). Internally, the
  18. voyager has a dual arbitrated system bus and a configuration and test
  19. bus (CAT). The voyager bus speed is 40MHz. Therefore (since all
  20. voyager cards are dual ported for each system bus) the maximum
  21. transfer rate is 320Mb/s but only if you have your slot configuration
  22. tuned (only memory cards can communicate with both busses at once, CPU
  23. cards utilise them one at a time).
  24. Voyager SMP
  25. -----------
  26. Since voyager was the first intel based SMP system, it is slightly
  27. more primitive than the Intel IO-APIC approach to SMP. Voyager allows
  28. arbitrary interrupt routing (including processor affinity routing) of
  29. all 16 PC type interrupts. However it does this by using a modified
  30. 5259 master/slave chip set instead of an APIC bus. Additionally,
  31. voyager supports Cross Processor Interrupts (CPI) equivalent to the
  32. APIC IPIs. There are two routed voyager interrupt lines provided to
  33. each slot.
  34. Processor Cards
  35. ---------------
  36. These come in single, dyadic and quad configurations (the quads are
  37. problematic--see later). The maximum configuration is 8 quad cards
  38. for 32 way SMP.
  39. Quad Processors
  40. ---------------
  41. Because voyager only supplies two interrupt lines to each Processor
  42. card, the Quad processors have to be configured (and Bootstrapped) in
  43. as a pair of Master/Slave processors.
  44. In fact, most Quad cards only accept one VIC interrupt line, so they
  45. have one interrupt handling processor (called the VIC extended
  46. processor) and three non-interrupt handling processors.
  47. Current Status
  48. --------------
  49. The System will boot on Mono, Dyad and Quad cards. There was
  50. originally a Quad boot problem which has been fixed by proper gdt
  51. alignment in the initial boot loader. If you still cannot get your
  52. voyager system to boot, email me at:
  53. <J.E.J.Bottomley@HansenPartnership.com>
  54. The Quad cards now support using the separate Quad CPI vectors instead
  55. of going through the VIC mailbox system.
  56. The Level 4 architecture (3430 and 3360 Machines) should also work
  57. fine.
  58. Dump Switch
  59. -----------
  60. The voyager dump switch sends out a broadcast NMI which the voyager
  61. code intercepts and does a task dump.
  62. Power Switch
  63. ------------
  64. The front panel power switch is intercepted by the kernel and should
  65. cause a system shutdown and power off.
  66. A Note About Mixed CPU Systems
  67. ------------------------------
  68. Linux isn't designed to handle mixed CPU systems very well. In order
  69. to get everything going you *must* make sure that your lowest
  70. capability CPU is used for booting. Also, mixing CPU classes
  71. (e.g. 486 and 586) is really not going to work very well at all.