SBC8260_memory_mapping.txt 7.9 KB

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  1. Please mail me (Jon Diekema, diekema_jon@si.com or diekema@cideas.com)
  2. if you have questions, comments or corrections.
  3. * EST SBC8260 Linux memory mapping rules
  4. http://www.estc.com/
  5. http://www.estc.com/products/boards/SBC8260-8240_ds.html
  6. Initial conditions:
  7. -------------------
  8. Tasks that need to be perform by the boot ROM before control is
  9. transferred to zImage (compressed Linux kernel):
  10. - Define the IMMR to 0xf0000000
  11. - Initialize the memory controller so that RAM is available at
  12. physical address 0x00000000. On the SBC8260 is this 16M (64M)
  13. SDRAM.
  14. - The boot ROM should only clear the RAM that it is using.
  15. The reason for doing this is to enhances the chances of a
  16. successful post mortem on a Linux panic. One of the first
  17. items to examine is the 16k (LOG_BUF_LEN) circular console
  18. buffer called log_buf which is defined in kernel/printk.c.
  19. - To enhance boot ROM performance, the I-cache can be enabled.
  20. Date: Mon, 22 May 2000 14:21:10 -0700
  21. From: Neil Russell <caret@c-side.com>
  22. LiMon (LInux MONitor) runs with and starts Linux with MMU
  23. off, I-cache enabled, D-cache disabled. The I-cache doesn't
  24. need hints from the MMU to work correctly as the D-cache
  25. does. No D-cache means no special code to handle devices in
  26. the presence of cache (no snooping, etc). The use of the
  27. I-cache means that the monitor can run acceptably fast
  28. directly from ROM, rather than having to copy it to RAM.
  29. - Build the board information structure (see
  30. include/asm-ppc/est8260.h for its definition)
  31. - The compressed Linux kernel (zImage) contains a bootstrap loader
  32. that is position independent; you can load it into any RAM,
  33. ROM or FLASH memory address >= 0x00500000 (above 5 MB), or
  34. at its link address of 0x00400000 (4 MB).
  35. Note: If zImage is loaded at its link address of 0x00400000 (4 MB),
  36. then zImage will skip the step of moving itself to
  37. its link address.
  38. - Load R3 with the address of the board information structure
  39. - Transfer control to zImage
  40. - The Linux console port is SMC1, and the baud rate is controlled
  41. from the bi_baudrate field of the board information structure.
  42. On thing to keep in mind when picking the baud rate, is that
  43. there is no flow control on the SMC ports. I would stick
  44. with something safe and standard like 19200.
  45. On the EST SBC8260, the SMC1 port is on the COM1 connector of
  46. the board.
  47. EST SBC8260 defaults:
  48. ---------------------
  49. Chip
  50. Memory Sel Bus Use
  51. --------------------- --- --- ----------------------------------
  52. 0x00000000-0x03FFFFFF CS2 60x (16M or 64M)/64M SDRAM
  53. 0x04000000-0x04FFFFFF CS4 local 4M/16M SDRAM (soldered to the board)
  54. 0x21000000-0x21000000 CS7 60x 1B/64K Flash present detect (from the flash SIMM)
  55. 0x21000001-0x21000001 CS7 60x 1B/64K Switches (read) and LEDs (write)
  56. 0x22000000-0x2200FFFF CS5 60x 8K/64K EEPROM
  57. 0xFC000000-0xFCFFFFFF CS6 60x 2M/16M flash (8 bits wide, soldered to the board)
  58. 0xFE000000-0xFFFFFFFF CS0 60x 4M/16M flash (SIMM)
  59. Notes:
  60. ------
  61. - The chip selects can map 32K blocks and up (powers of 2)
  62. - The SDRAM machine can handled up to 128Mbytes per chip select
  63. - Linux uses the 60x bus memory (the SDRAM DIMM) for the
  64. communications buffers.
  65. - BATs can map 128K-256Mbytes each. There are four data BATs and
  66. four instruction BATs. Generally the data and instruction BATs
  67. are mapped the same.
  68. - The IMMR must be set above the kernel virtual memory addresses,
  69. which start at 0xC0000000. Otherwise, the kernel may crash as
  70. soon as you start any threads or processes due to VM collisions
  71. in the kernel or user process space.
  72. Details from Dan Malek <dan_malek@mvista.com> on 10/29/1999:
  73. The user application virtual space consumes the first 2 Gbytes
  74. (0x00000000 to 0x7FFFFFFF). The kernel virtual text starts at
  75. 0xC0000000, with data following. There is a "protection hole"
  76. between the end of kernel data and the start of the kernel
  77. dynamically allocated space, but this space is still within
  78. 0xCxxxxxxx.
  79. Obviously the kernel can't map any physical addresses 1:1 in
  80. these ranges.
  81. Details from Dan Malek <dan_malek@mvista.com> on 5/19/2000:
  82. During the early kernel initialization, the kernel virtual
  83. memory allocator is not operational. Prior to this KVM
  84. initialization, we choose to map virtual to physical addresses
  85. 1:1. That is, the kernel virtual address exactly matches the
  86. physical address on the bus. These mappings are typically done
  87. in arch/ppc/kernel/head.S, or arch/ppc/mm/init.c. Only
  88. absolutely necessary mappings should be done at this time, for
  89. example board control registers or a serial uart. Normal device
  90. driver initialization should map resources later when necessary.
  91. Although platform dependent, and certainly the case for embedded
  92. 8xx, traditionally memory is mapped at physical address zero,
  93. and I/O devices above physical address 0x80000000. The lowest
  94. and highest (above 0xf0000000) I/O addresses are traditionally
  95. used for devices or registers we need to map during kernel
  96. initialization and prior to KVM operation. For this reason,
  97. and since it followed prior PowerPC platform examples, I chose
  98. to map the embedded 8xx kernel to the 0xc0000000 virtual address.
  99. This way, we can enable the MMU to map the kernel for proper
  100. operation, and still map a few windows before the KVM is operational.
  101. On some systems, you could possibly run the kernel at the
  102. 0x80000000 or any other virtual address. It just depends upon
  103. mapping that must be done prior to KVM operational. You can never
  104. map devices or kernel spaces that overlap with the user virtual
  105. space. This is why default IMMR mapping used by most BDM tools
  106. won't work. They put the IMMR at something like 0x10000000 or
  107. 0x02000000 for example. You simply can't map these addresses early
  108. in the kernel, and continue proper system operation.
  109. The embedded 8xx/82xx kernel is mature enough that all you should
  110. need to do is map the IMMR someplace at or above 0xf0000000 and it
  111. should boot far enough to get serial console messages and KGDB
  112. connected on any platform. There are lots of other subtle memory
  113. management design features that you simply don't need to worry
  114. about. If you are changing functions related to MMU initialization,
  115. you are likely breaking things that are known to work and are
  116. heading down a path of disaster and frustration. Your changes
  117. should be to make the flexibility of the processor fit Linux,
  118. not force arbitrary and non-workable memory mappings into Linux.
  119. - You don't want to change KERNELLOAD or KERNELBASE, otherwise the
  120. virtual memory and MMU code will get confused.
  121. arch/ppc/Makefile:KERNELLOAD = 0xc0000000
  122. include/asm-ppc/page.h:#define PAGE_OFFSET 0xc0000000
  123. include/asm-ppc/page.h:#define KERNELBASE PAGE_OFFSET
  124. - RAM is at physical address 0x00000000, and gets mapped to
  125. virtual address 0xC0000000 for the kernel.
  126. Physical addresses used by the Linux kernel:
  127. --------------------------------------------
  128. 0x00000000-0x3FFFFFFF 1GB reserved for RAM
  129. 0xF0000000-0xF001FFFF 128K IMMR 64K used for dual port memory,
  130. 64K for 8260 registers
  131. Logical addresses used by the Linux kernel:
  132. -------------------------------------------
  133. 0xF0000000-0xFFFFFFFF 256M BAT0 (IMMR: dual port RAM, registers)
  134. 0xE0000000-0xEFFFFFFF 256M BAT1 (I/O space for custom boards)
  135. 0xC0000000-0xCFFFFFFF 256M BAT2 (RAM)
  136. 0xD0000000-0xDFFFFFFF 256M BAT3 (if RAM > 256MByte)
  137. EST SBC8260 Linux mapping:
  138. --------------------------
  139. DBAT0, IBAT0, cache inhibited:
  140. Chip
  141. Memory Sel Use
  142. --------------------- --- ---------------------------------
  143. 0xF0000000-0xF001FFFF n/a IMMR: dual port RAM, registers
  144. DBAT1, IBAT1, cache inhibited: