pci-error-recovery.txt 18 KB

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  1. PCI Error Recovery
  2. ------------------
  3. February 2, 2006
  4. Current document maintainer:
  5. Linas Vepstas <linas@austin.ibm.com>
  6. Many PCI bus controllers are able to detect a variety of hardware
  7. PCI errors on the bus, such as parity errors on the data and address
  8. busses, as well as SERR and PERR errors. Some of the more advanced
  9. chipsets are able to deal with these errors; these include PCI-E chipsets,
  10. and the PCI-host bridges found on IBM Power4 and Power5-based pSeries
  11. boxes. A typical action taken is to disconnect the affected device,
  12. halting all I/O to it. The goal of a disconnection is to avoid system
  13. corruption; for example, to halt system memory corruption due to DMA's
  14. to "wild" addresses. Typically, a reconnection mechanism is also
  15. offered, so that the affected PCI device(s) are reset and put back
  16. into working condition. The reset phase requires coordination
  17. between the affected device drivers and the PCI controller chip.
  18. This document describes a generic API for notifying device drivers
  19. of a bus disconnection, and then performing error recovery.
  20. This API is currently implemented in the 2.6.16 and later kernels.
  21. Reporting and recovery is performed in several steps. First, when
  22. a PCI hardware error has resulted in a bus disconnect, that event
  23. is reported as soon as possible to all affected device drivers,
  24. including multiple instances of a device driver on multi-function
  25. cards. This allows device drivers to avoid deadlocking in spinloops,
  26. waiting for some i/o-space register to change, when it never will.
  27. It also gives the drivers a chance to defer incoming I/O as
  28. needed.
  29. Next, recovery is performed in several stages. Most of the complexity
  30. is forced by the need to handle multi-function devices, that is,
  31. devices that have multiple device drivers associated with them.
  32. In the first stage, each driver is allowed to indicate what type
  33. of reset it desires, the choices being a simple re-enabling of I/O
  34. or requesting a hard reset (a full electrical #RST of the PCI card).
  35. If any driver requests a full reset, that is what will be done.
  36. After a full reset and/or a re-enabling of I/O, all drivers are
  37. again notified, so that they may then perform any device setup/config
  38. that may be required. After these have all completed, a final
  39. "resume normal operations" event is sent out.
  40. The biggest reason for choosing a kernel-based implementation rather
  41. than a user-space implementation was the need to deal with bus
  42. disconnects of PCI devices attached to storage media, and, in particular,
  43. disconnects from devices holding the root file system. If the root
  44. file system is disconnected, a user-space mechanism would have to go
  45. through a large number of contortions to complete recovery. Almost all
  46. of the current Linux file systems are not tolerant of disconnection
  47. from/reconnection to their underlying block device. By contrast,
  48. bus errors are easy to manage in the device driver. Indeed, most
  49. device drivers already handle very similar recovery procedures;
  50. for example, the SCSI-generic layer already provides significant
  51. mechanisms for dealing with SCSI bus errors and SCSI bus resets.
  52. Detailed Design
  53. ---------------
  54. Design and implementation details below, based on a chain of
  55. public email discussions with Ben Herrenschmidt, circa 5 April 2005.
  56. The error recovery API support is exposed to the driver in the form of
  57. a structure of function pointers pointed to by a new field in struct
  58. pci_driver. A driver that fails to provide the structure is "non-aware",
  59. and the actual recovery steps taken are platform dependent. The
  60. arch/powerpc implementation will simulate a PCI hotplug remove/add.
  61. This structure has the form:
  62. struct pci_error_handlers
  63. {
  64. int (*error_detected)(struct pci_dev *dev, enum pci_channel_state);
  65. int (*mmio_enabled)(struct pci_dev *dev);
  66. int (*link_reset)(struct pci_dev *dev);
  67. int (*slot_reset)(struct pci_dev *dev);
  68. void (*resume)(struct pci_dev *dev);
  69. };
  70. The possible channel states are:
  71. enum pci_channel_state {
  72. pci_channel_io_normal, /* I/O channel is in normal state */
  73. pci_channel_io_frozen, /* I/O to channel is blocked */
  74. pci_channel_io_perm_failure, /* PCI card is dead */
  75. };
  76. Possible return values are:
  77. enum pci_ers_result {
  78. PCI_ERS_RESULT_NONE, /* no result/none/not supported in device driver */
  79. PCI_ERS_RESULT_CAN_RECOVER, /* Device driver can recover without slot reset */
  80. PCI_ERS_RESULT_NEED_RESET, /* Device driver wants slot to be reset. */
  81. PCI_ERS_RESULT_DISCONNECT, /* Device has completely failed, is unrecoverable */
  82. PCI_ERS_RESULT_RECOVERED, /* Device driver is fully recovered and operational */
  83. };
  84. A driver does not have to implement all of these callbacks; however,
  85. if it implements any, it must implement error_detected(). If a callback
  86. is not implemented, the corresponding feature is considered unsupported.
  87. For example, if mmio_enabled() and resume() aren't there, then it
  88. is assumed that the driver is not doing any direct recovery and requires
  89. a reset. If link_reset() is not implemented, the card is assumed as
  90. not care about link resets. Typically a driver will want to know about
  91. a slot_reset().
  92. The actual steps taken by a platform to recover from a PCI error
  93. event will be platform-dependent, but will follow the general
  94. sequence described below.
  95. STEP 0: Error Event
  96. -------------------
  97. PCI bus error is detect by the PCI hardware. On powerpc, the slot
  98. is isolated, in that all I/O is blocked: all reads return 0xffffffff,
  99. all writes are ignored.
  100. STEP 1: Notification
  101. --------------------
  102. Platform calls the error_detected() callback on every instance of
  103. every driver affected by the error.
  104. At this point, the device might not be accessible anymore, depending on
  105. the platform (the slot will be isolated on powerpc). The driver may
  106. already have "noticed" the error because of a failing I/O, but this
  107. is the proper "synchronization point", that is, it gives the driver
  108. a chance to cleanup, waiting for pending stuff (timers, whatever, etc...)
  109. to complete; it can take semaphores, schedule, etc... everything but
  110. touch the device. Within this function and after it returns, the driver
  111. shouldn't do any new IOs. Called in task context. This is sort of a
  112. "quiesce" point. See note about interrupts at the end of this doc.
  113. All drivers participating in this system must implement this call.
  114. The driver must return one of the following result codes:
  115. - PCI_ERS_RESULT_CAN_RECOVER:
  116. Driver returns this if it thinks it might be able to recover
  117. the HW by just banging IOs or if it wants to be given
  118. a chance to extract some diagnostic information (see
  119. mmio_enable, below).
  120. - PCI_ERS_RESULT_NEED_RESET:
  121. Driver returns this if it can't recover without a hard
  122. slot reset.
  123. - PCI_ERS_RESULT_DISCONNECT:
  124. Driver returns this if it doesn't want to recover at all.
  125. The next step taken will depend on the result codes returned by the
  126. drivers.
  127. If all drivers on the segment/slot return PCI_ERS_RESULT_CAN_RECOVER,
  128. then the platform should re-enable IOs on the slot (or do nothing in
  129. particular, if the platform doesn't isolate slots), and recovery
  130. proceeds to STEP 2 (MMIO Enable).
  131. If any driver requested a slot reset (by returning PCI_ERS_RESULT_NEED_RESET),
  132. then recovery proceeds to STEP 4 (Slot Reset).
  133. If the platform is unable to recover the slot, the next step
  134. is STEP 6 (Permanent Failure).
  135. >>> The current powerpc implementation assumes that a device driver will
  136. >>> *not* schedule or semaphore in this routine; the current powerpc
  137. >>> implementation uses one kernel thread to notify all devices;
  138. >>> thus, if one device sleeps/schedules, all devices are affected.
  139. >>> Doing better requires complex multi-threaded logic in the error
  140. >>> recovery implementation (e.g. waiting for all notification threads
  141. >>> to "join" before proceeding with recovery.) This seems excessively
  142. >>> complex and not worth implementing.
  143. >>> The current powerpc implementation doesn't much care if the device
  144. >>> attempts I/O at this point, or not. I/O's will fail, returning
  145. >>> a value of 0xff on read, and writes will be dropped. If the device
  146. >>> driver attempts more than 10K I/O's to a frozen adapter, it will
  147. >>> assume that the device driver has gone into an infinite loop, and
  148. >>> it will panic the kernel. There doesn't seem to be any other
  149. >>> way of stopping a device driver that insists on spinning on I/O.
  150. STEP 2: MMIO Enabled
  151. -------------------
  152. The platform re-enables MMIO to the device (but typically not the
  153. DMA), and then calls the mmio_enabled() callback on all affected
  154. device drivers.
  155. This is the "early recovery" call. IOs are allowed again, but DMA is
  156. not (hrm... to be discussed, I prefer not), with some restrictions. This
  157. is NOT a callback for the driver to start operations again, only to
  158. peek/poke at the device, extract diagnostic information, if any, and
  159. eventually do things like trigger a device local reset or some such,
  160. but not restart operations. This is callback is made if all drivers on
  161. a segment agree that they can try to recover and if no automatic link reset
  162. was performed by the HW. If the platform can't just re-enable IOs without
  163. a slot reset or a link reset, it wont call this callback, and instead
  164. will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot Reset)
  165. >>> The following is proposed; no platform implements this yet:
  166. >>> Proposal: All I/O's should be done _synchronously_ from within
  167. >>> this callback, errors triggered by them will be returned via
  168. >>> the normal pci_check_whatever() API, no new error_detected()
  169. >>> callback will be issued due to an error happening here. However,
  170. >>> such an error might cause IOs to be re-blocked for the whole
  171. >>> segment, and thus invalidate the recovery that other devices
  172. >>> on the same segment might have done, forcing the whole segment
  173. >>> into one of the next states, that is, link reset or slot reset.
  174. The driver should return one of the following result codes:
  175. - PCI_ERS_RESULT_RECOVERED
  176. Driver returns this if it thinks the device is fully
  177. functional and thinks it is ready to start
  178. normal driver operations again. There is no
  179. guarantee that the driver will actually be
  180. allowed to proceed, as another driver on the
  181. same segment might have failed and thus triggered a
  182. slot reset on platforms that support it.
  183. - PCI_ERS_RESULT_NEED_RESET
  184. Driver returns this if it thinks the device is not
  185. recoverable in it's current state and it needs a slot
  186. reset to proceed.
  187. - PCI_ERS_RESULT_DISCONNECT
  188. Same as above. Total failure, no recovery even after
  189. reset driver dead. (To be defined more precisely)
  190. The next step taken depends on the results returned by the drivers.
  191. If all drivers returned PCI_ERS_RESULT_RECOVERED, then the platform
  192. proceeds to either STEP3 (Link Reset) or to STEP 5 (Resume Operations).
  193. If any driver returned PCI_ERS_RESULT_NEED_RESET, then the platform
  194. proceeds to STEP 4 (Slot Reset)
  195. >>> The current powerpc implementation does not implement this callback.
  196. STEP 3: Link Reset
  197. ------------------
  198. The platform resets the link, and then calls the link_reset() callback
  199. on all affected device drivers. This is a PCI-Express specific state
  200. and is done whenever a non-fatal error has been detected that can be
  201. "solved" by resetting the link. This call informs the driver of the
  202. reset and the driver should check to see if the device appears to be
  203. in working condition.
  204. The driver is not supposed to restart normal driver I/O operations
  205. at this point. It should limit itself to "probing" the device to
  206. check it's recoverability status. If all is right, then the platform
  207. will call resume() once all drivers have ack'd link_reset().
  208. Result codes:
  209. (identical to STEP 3 (MMIO Enabled)
  210. The platform then proceeds to either STEP 4 (Slot Reset) or STEP 5
  211. (Resume Operations).
  212. >>> The current powerpc implementation does not implement this callback.
  213. STEP 4: Slot Reset
  214. ------------------
  215. The platform performs a soft or hard reset of the device, and then
  216. calls the slot_reset() callback.
  217. A soft reset consists of asserting the adapter #RST line and then
  218. restoring the PCI BAR's and PCI configuration header to a state
  219. that is equivalent to what it would be after a fresh system
  220. power-on followed by power-on BIOS/system firmware initialization.
  221. If the platform supports PCI hotplug, then the reset might be
  222. performed by toggling the slot electrical power off/on.
  223. It is important for the platform to restore the PCI config space
  224. to the "fresh poweron" state, rather than the "last state". After
  225. a slot reset, the device driver will almost always use its standard
  226. device initialization routines, and an unusual config space setup
  227. may result in hung devices, kernel panics, or silent data corruption.
  228. This call gives drivers the chance to re-initialize the hardware
  229. (re-download firmware, etc.). At this point, the driver may assume
  230. that he card is in a fresh state and is fully functional. In
  231. particular, interrupt generation should work normally.
  232. Drivers should not yet restart normal I/O processing operations
  233. at this point. If all device drivers report success on this
  234. callback, the platform will call resume() to complete the sequence,
  235. and let the driver restart normal I/O processing.
  236. A driver can still return a critical failure for this function if
  237. it can't get the device operational after reset. If the platform
  238. previously tried a soft reset, it might now try a hard reset (power
  239. cycle) and then call slot_reset() again. It the device still can't
  240. be recovered, there is nothing more that can be done; the platform
  241. will typically report a "permanent failure" in such a case. The
  242. device will be considered "dead" in this case.
  243. Drivers for multi-function cards will need to coordinate among
  244. themselves as to which driver instance will perform any "one-shot"
  245. or global device initialization. For example, the Symbios sym53cxx2
  246. driver performs device init only from PCI function 0:
  247. + if (PCI_FUNC(pdev->devfn) == 0)
  248. + sym_reset_scsi_bus(np, 0);
  249. Result codes:
  250. - PCI_ERS_RESULT_DISCONNECT
  251. Same as above.
  252. Platform proceeds either to STEP 5 (Resume Operations) or STEP 6 (Permanent
  253. Failure).
  254. >>> The current powerpc implementation does not currently try a
  255. >>> power-cycle reset if the driver returned PCI_ERS_RESULT_DISCONNECT.
  256. >>> However, it probably should.
  257. STEP 5: Resume Operations
  258. -------------------------
  259. The platform will call the resume() callback on all affected device
  260. drivers if all drivers on the segment have returned
  261. PCI_ERS_RESULT_RECOVERED from one of the 3 previous callbacks.
  262. The goal of this callback is to tell the driver to restart activity,
  263. that everything is back and running. This callback does not return
  264. a result code.
  265. At this point, if a new error happens, the platform will restart
  266. a new error recovery sequence.
  267. STEP 6: Permanent Failure
  268. -------------------------
  269. A "permanent failure" has occurred, and the platform cannot recover
  270. the device. The platform will call error_detected() with a
  271. pci_channel_state value of pci_channel_io_perm_failure.
  272. The device driver should, at this point, assume the worst. It should
  273. cancel all pending I/O, refuse all new I/O, returning -EIO to
  274. higher layers. The device driver should then clean up all of its
  275. memory and remove itself from kernel operations, much as it would
  276. during system shutdown.
  277. The platform will typically notify the system operator of the
  278. permanent failure in some way. If the device is hotplug-capable,
  279. the operator will probably want to remove and replace the device.
  280. Note, however, not all failures are truly "permanent". Some are
  281. caused by over-heating, some by a poorly seated card. Many
  282. PCI error events are caused by software bugs, e.g. DMA's to
  283. wild addresses or bogus split transactions due to programming
  284. errors. See the discussion in powerpc/eeh-pci-error-recovery.txt
  285. for additional detail on real-life experience of the causes of
  286. software errors.
  287. Conclusion; General Remarks
  288. ---------------------------
  289. The way those callbacks are called is platform policy. A platform with
  290. no slot reset capability may want to just "ignore" drivers that can't
  291. recover (disconnect them) and try to let other cards on the same segment
  292. recover. Keep in mind that in most real life cases, though, there will
  293. be only one driver per segment.
  294. Now, a note about interrupts. If you get an interrupt and your
  295. device is dead or has been isolated, there is a problem :)
  296. The current policy is to turn this into a platform policy.
  297. That is, the recovery API only requires that:
  298. - There is no guarantee that interrupt delivery can proceed from any
  299. device on the segment starting from the error detection and until the
  300. resume callback is sent, at which point interrupts are expected to be
  301. fully operational.
  302. - There is no guarantee that interrupt delivery is stopped, that is,
  303. a driver that gets an interrupt after detecting an error, or that detects
  304. an error within the interrupt handler such that it prevents proper
  305. ack'ing of the interrupt (and thus removal of the source) should just
  306. return IRQ_NOTHANDLED. It's up to the platform to deal with that
  307. condition, typically by masking the IRQ source during the duration of
  308. the error handling. It is expected that the platform "knows" which
  309. interrupts are routed to error-management capable slots and can deal
  310. with temporarily disabling that IRQ number during error processing (this
  311. isn't terribly complex). That means some IRQ latency for other devices
  312. sharing the interrupt, but there is simply no other way. High end
  313. platforms aren't supposed to share interrupts between many devices
  314. anyway :)
  315. >>> Implementation details for the powerpc platform are discussed in
  316. >>> the file Documentation/powerpc/eeh-pci-error-recovery.txt
  317. >>> As of this writing, there are six device drivers with patches
  318. >>> implementing error recovery. Not all of these patches are in
  319. >>> mainline yet. These may be used as "examples":
  320. >>>
  321. >>> drivers/scsi/ipr.c
  322. >>> drivers/scsi/sym53cxx_2
  323. >>> drivers/next/e100.c
  324. >>> drivers/net/e1000
  325. >>> drivers/net/ixgb
  326. >>> drivers/net/s2io.c
  327. The End
  328. -------