memory-barriers.txt 75 KB

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  1. ============================
  2. LINUX KERNEL MEMORY BARRIERS
  3. ============================
  4. By: David Howells <dhowells@redhat.com>
  5. Contents:
  6. (*) Abstract memory access model.
  7. - Device operations.
  8. - Guarantees.
  9. (*) What are memory barriers?
  10. - Varieties of memory barrier.
  11. - What may not be assumed about memory barriers?
  12. - Data dependency barriers.
  13. - Control dependencies.
  14. - SMP barrier pairing.
  15. - Examples of memory barrier sequences.
  16. - Read memory barriers vs load speculation.
  17. (*) Explicit kernel barriers.
  18. - Compiler barrier.
  19. - The CPU memory barriers.
  20. - MMIO write barrier.
  21. (*) Implicit kernel memory barriers.
  22. - Locking functions.
  23. - Interrupt disabling functions.
  24. - Miscellaneous functions.
  25. (*) Inter-CPU locking barrier effects.
  26. - Locks vs memory accesses.
  27. - Locks vs I/O accesses.
  28. (*) Where are memory barriers needed?
  29. - Interprocessor interaction.
  30. - Atomic operations.
  31. - Accessing devices.
  32. - Interrupts.
  33. (*) Kernel I/O barrier effects.
  34. (*) Assumed minimum execution ordering model.
  35. (*) The effects of the cpu cache.
  36. - Cache coherency.
  37. - Cache coherency vs DMA.
  38. - Cache coherency vs MMIO.
  39. (*) The things CPUs get up to.
  40. - And then there's the Alpha.
  41. (*) References.
  42. ============================
  43. ABSTRACT MEMORY ACCESS MODEL
  44. ============================
  45. Consider the following abstract model of the system:
  46. : :
  47. : :
  48. : :
  49. +-------+ : +--------+ : +-------+
  50. | | : | | : | |
  51. | | : | | : | |
  52. | CPU 1 |<----->| Memory |<----->| CPU 2 |
  53. | | : | | : | |
  54. | | : | | : | |
  55. +-------+ : +--------+ : +-------+
  56. ^ : ^ : ^
  57. | : | : |
  58. | : | : |
  59. | : v : |
  60. | : +--------+ : |
  61. | : | | : |
  62. | : | | : |
  63. +---------->| Device |<----------+
  64. : | | :
  65. : | | :
  66. : +--------+ :
  67. : :
  68. Each CPU executes a program that generates memory access operations. In the
  69. abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
  70. perform the memory operations in any order it likes, provided program causality
  71. appears to be maintained. Similarly, the compiler may also arrange the
  72. instructions it emits in any order it likes, provided it doesn't affect the
  73. apparent operation of the program.
  74. So in the above diagram, the effects of the memory operations performed by a
  75. CPU are perceived by the rest of the system as the operations cross the
  76. interface between the CPU and rest of the system (the dotted lines).
  77. For example, consider the following sequence of events:
  78. CPU 1 CPU 2
  79. =============== ===============
  80. { A == 1; B == 2 }
  81. A = 3; x = A;
  82. B = 4; y = B;
  83. The set of accesses as seen by the memory system in the middle can be arranged
  84. in 24 different combinations:
  85. STORE A=3, STORE B=4, x=LOAD A->3, y=LOAD B->4
  86. STORE A=3, STORE B=4, y=LOAD B->4, x=LOAD A->3
  87. STORE A=3, x=LOAD A->3, STORE B=4, y=LOAD B->4
  88. STORE A=3, x=LOAD A->3, y=LOAD B->2, STORE B=4
  89. STORE A=3, y=LOAD B->2, STORE B=4, x=LOAD A->3
  90. STORE A=3, y=LOAD B->2, x=LOAD A->3, STORE B=4
  91. STORE B=4, STORE A=3, x=LOAD A->3, y=LOAD B->4
  92. STORE B=4, ...
  93. ...
  94. and can thus result in four different combinations of values:
  95. x == 1, y == 2
  96. x == 1, y == 4
  97. x == 3, y == 2
  98. x == 3, y == 4
  99. Furthermore, the stores committed by a CPU to the memory system may not be
  100. perceived by the loads made by another CPU in the same order as the stores were
  101. committed.
  102. As a further example, consider this sequence of events:
  103. CPU 1 CPU 2
  104. =============== ===============
  105. { A == 1, B == 2, C = 3, P == &A, Q == &C }
  106. B = 4; Q = P;
  107. P = &B D = *Q;
  108. There is an obvious data dependency here, as the value loaded into D depends on
  109. the address retrieved from P by CPU 2. At the end of the sequence, any of the
  110. following results are possible:
  111. (Q == &A) and (D == 1)
  112. (Q == &B) and (D == 2)
  113. (Q == &B) and (D == 4)
  114. Note that CPU 2 will never try and load C into D because the CPU will load P
  115. into Q before issuing the load of *Q.
  116. DEVICE OPERATIONS
  117. -----------------
  118. Some devices present their control interfaces as collections of memory
  119. locations, but the order in which the control registers are accessed is very
  120. important. For instance, imagine an ethernet card with a set of internal
  121. registers that are accessed through an address port register (A) and a data
  122. port register (D). To read internal register 5, the following code might then
  123. be used:
  124. *A = 5;
  125. x = *D;
  126. but this might show up as either of the following two sequences:
  127. STORE *A = 5, x = LOAD *D
  128. x = LOAD *D, STORE *A = 5
  129. the second of which will almost certainly result in a malfunction, since it set
  130. the address _after_ attempting to read the register.
  131. GUARANTEES
  132. ----------
  133. There are some minimal guarantees that may be expected of a CPU:
  134. (*) On any given CPU, dependent memory accesses will be issued in order, with
  135. respect to itself. This means that for:
  136. Q = P; D = *Q;
  137. the CPU will issue the following memory operations:
  138. Q = LOAD P, D = LOAD *Q
  139. and always in that order.
  140. (*) Overlapping loads and stores within a particular CPU will appear to be
  141. ordered within that CPU. This means that for:
  142. a = *X; *X = b;
  143. the CPU will only issue the following sequence of memory operations:
  144. a = LOAD *X, STORE *X = b
  145. And for:
  146. *X = c; d = *X;
  147. the CPU will only issue:
  148. STORE *X = c, d = LOAD *X
  149. (Loads and stores overlap if they are targeted at overlapping pieces of
  150. memory).
  151. And there are a number of things that _must_ or _must_not_ be assumed:
  152. (*) It _must_not_ be assumed that independent loads and stores will be issued
  153. in the order given. This means that for:
  154. X = *A; Y = *B; *D = Z;
  155. we may get any of the following sequences:
  156. X = LOAD *A, Y = LOAD *B, STORE *D = Z
  157. X = LOAD *A, STORE *D = Z, Y = LOAD *B
  158. Y = LOAD *B, X = LOAD *A, STORE *D = Z
  159. Y = LOAD *B, STORE *D = Z, X = LOAD *A
  160. STORE *D = Z, X = LOAD *A, Y = LOAD *B
  161. STORE *D = Z, Y = LOAD *B, X = LOAD *A
  162. (*) It _must_ be assumed that overlapping memory accesses may be merged or
  163. discarded. This means that for:
  164. X = *A; Y = *(A + 4);
  165. we may get any one of the following sequences:
  166. X = LOAD *A; Y = LOAD *(A + 4);
  167. Y = LOAD *(A + 4); X = LOAD *A;
  168. {X, Y} = LOAD {*A, *(A + 4) };
  169. And for:
  170. *A = X; Y = *A;
  171. we may get either of:
  172. STORE *A = X; Y = LOAD *A;
  173. STORE *A = Y = X;
  174. =========================
  175. WHAT ARE MEMORY BARRIERS?
  176. =========================
  177. As can be seen above, independent memory operations are effectively performed
  178. in random order, but this can be a problem for CPU-CPU interaction and for I/O.
  179. What is required is some way of intervening to instruct the compiler and the
  180. CPU to restrict the order.
  181. Memory barriers are such interventions. They impose a perceived partial
  182. ordering over the memory operations on either side of the barrier.
  183. Such enforcement is important because the CPUs and other devices in a system
  184. can use a variety of tricks to improve performance - including reordering,
  185. deferral and combination of memory operations; speculative loads; speculative
  186. branch prediction and various types of caching. Memory barriers are used to
  187. override or suppress these tricks, allowing the code to sanely control the
  188. interaction of multiple CPUs and/or devices.
  189. VARIETIES OF MEMORY BARRIER
  190. ---------------------------
  191. Memory barriers come in four basic varieties:
  192. (1) Write (or store) memory barriers.
  193. A write memory barrier gives a guarantee that all the STORE operations
  194. specified before the barrier will appear to happen before all the STORE
  195. operations specified after the barrier with respect to the other
  196. components of the system.
  197. A write barrier is a partial ordering on stores only; it is not required
  198. to have any effect on loads.
  199. A CPU can be viewed as committing a sequence of store operations to the
  200. memory system as time progresses. All stores before a write barrier will
  201. occur in the sequence _before_ all the stores after the write barrier.
  202. [!] Note that write barriers should normally be paired with read or data
  203. dependency barriers; see the "SMP barrier pairing" subsection.
  204. (2) Data dependency barriers.
  205. A data dependency barrier is a weaker form of read barrier. In the case
  206. where two loads are performed such that the second depends on the result
  207. of the first (eg: the first load retrieves the address to which the second
  208. load will be directed), a data dependency barrier would be required to
  209. make sure that the target of the second load is updated before the address
  210. obtained by the first load is accessed.
  211. A data dependency barrier is a partial ordering on interdependent loads
  212. only; it is not required to have any effect on stores, independent loads
  213. or overlapping loads.
  214. As mentioned in (1), the other CPUs in the system can be viewed as
  215. committing sequences of stores to the memory system that the CPU being
  216. considered can then perceive. A data dependency barrier issued by the CPU
  217. under consideration guarantees that for any load preceding it, if that
  218. load touches one of a sequence of stores from another CPU, then by the
  219. time the barrier completes, the effects of all the stores prior to that
  220. touched by the load will be perceptible to any loads issued after the data
  221. dependency barrier.
  222. See the "Examples of memory barrier sequences" subsection for diagrams
  223. showing the ordering constraints.
  224. [!] Note that the first load really has to have a _data_ dependency and
  225. not a control dependency. If the address for the second load is dependent
  226. on the first load, but the dependency is through a conditional rather than
  227. actually loading the address itself, then it's a _control_ dependency and
  228. a full read barrier or better is required. See the "Control dependencies"
  229. subsection for more information.
  230. [!] Note that data dependency barriers should normally be paired with
  231. write barriers; see the "SMP barrier pairing" subsection.
  232. (3) Read (or load) memory barriers.
  233. A read barrier is a data dependency barrier plus a guarantee that all the
  234. LOAD operations specified before the barrier will appear to happen before
  235. all the LOAD operations specified after the barrier with respect to the
  236. other components of the system.
  237. A read barrier is a partial ordering on loads only; it is not required to
  238. have any effect on stores.
  239. Read memory barriers imply data dependency barriers, and so can substitute
  240. for them.
  241. [!] Note that read barriers should normally be paired with write barriers;
  242. see the "SMP barrier pairing" subsection.
  243. (4) General memory barriers.
  244. A general memory barrier gives a guarantee that all the LOAD and STORE
  245. operations specified before the barrier will appear to happen before all
  246. the LOAD and STORE operations specified after the barrier with respect to
  247. the other components of the system.
  248. A general memory barrier is a partial ordering over both loads and stores.
  249. General memory barriers imply both read and write memory barriers, and so
  250. can substitute for either.
  251. And a couple of implicit varieties:
  252. (5) LOCK operations.
  253. This acts as a one-way permeable barrier. It guarantees that all memory
  254. operations after the LOCK operation will appear to happen after the LOCK
  255. operation with respect to the other components of the system.
  256. Memory operations that occur before a LOCK operation may appear to happen
  257. after it completes.
  258. A LOCK operation should almost always be paired with an UNLOCK operation.
  259. (6) UNLOCK operations.
  260. This also acts as a one-way permeable barrier. It guarantees that all
  261. memory operations before the UNLOCK operation will appear to happen before
  262. the UNLOCK operation with respect to the other components of the system.
  263. Memory operations that occur after an UNLOCK operation may appear to
  264. happen before it completes.
  265. LOCK and UNLOCK operations are guaranteed to appear with respect to each
  266. other strictly in the order specified.
  267. The use of LOCK and UNLOCK operations generally precludes the need for
  268. other sorts of memory barrier (but note the exceptions mentioned in the
  269. subsection "MMIO write barrier").
  270. Memory barriers are only required where there's a possibility of interaction
  271. between two CPUs or between a CPU and a device. If it can be guaranteed that
  272. there won't be any such interaction in any particular piece of code, then
  273. memory barriers are unnecessary in that piece of code.
  274. Note that these are the _minimum_ guarantees. Different architectures may give
  275. more substantial guarantees, but they may _not_ be relied upon outside of arch
  276. specific code.
  277. WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
  278. ----------------------------------------------
  279. There are certain things that the Linux kernel memory barriers do not guarantee:
  280. (*) There is no guarantee that any of the memory accesses specified before a
  281. memory barrier will be _complete_ by the completion of a memory barrier
  282. instruction; the barrier can be considered to draw a line in that CPU's
  283. access queue that accesses of the appropriate type may not cross.
  284. (*) There is no guarantee that issuing a memory barrier on one CPU will have
  285. any direct effect on another CPU or any other hardware in the system. The
  286. indirect effect will be the order in which the second CPU sees the effects
  287. of the first CPU's accesses occur, but see the next point:
  288. (*) There is no guarantee that a CPU will see the correct order of effects
  289. from a second CPU's accesses, even _if_ the second CPU uses a memory
  290. barrier, unless the first CPU _also_ uses a matching memory barrier (see
  291. the subsection on "SMP Barrier Pairing").
  292. (*) There is no guarantee that some intervening piece of off-the-CPU
  293. hardware[*] will not reorder the memory accesses. CPU cache coherency
  294. mechanisms should propagate the indirect effects of a memory barrier
  295. between CPUs, but might not do so in order.
  296. [*] For information on bus mastering DMA and coherency please read:
  297. Documentation/pci.txt
  298. Documentation/DMA-mapping.txt
  299. Documentation/DMA-API.txt
  300. DATA DEPENDENCY BARRIERS
  301. ------------------------
  302. The usage requirements of data dependency barriers are a little subtle, and
  303. it's not always obvious that they're needed. To illustrate, consider the
  304. following sequence of events:
  305. CPU 1 CPU 2
  306. =============== ===============
  307. { A == 1, B == 2, C = 3, P == &A, Q == &C }
  308. B = 4;
  309. <write barrier>
  310. P = &B
  311. Q = P;
  312. D = *Q;
  313. There's a clear data dependency here, and it would seem that by the end of the
  314. sequence, Q must be either &A or &B, and that:
  315. (Q == &A) implies (D == 1)
  316. (Q == &B) implies (D == 4)
  317. But! CPU 2's perception of P may be updated _before_ its perception of B, thus
  318. leading to the following situation:
  319. (Q == &B) and (D == 2) ????
  320. Whilst this may seem like a failure of coherency or causality maintenance, it
  321. isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
  322. Alpha).
  323. To deal with this, a data dependency barrier or better must be inserted
  324. between the address load and the data load:
  325. CPU 1 CPU 2
  326. =============== ===============
  327. { A == 1, B == 2, C = 3, P == &A, Q == &C }
  328. B = 4;
  329. <write barrier>
  330. P = &B
  331. Q = P;
  332. <data dependency barrier>
  333. D = *Q;
  334. This enforces the occurrence of one of the two implications, and prevents the
  335. third possibility from arising.
  336. [!] Note that this extremely counterintuitive situation arises most easily on
  337. machines with split caches, so that, for example, one cache bank processes
  338. even-numbered cache lines and the other bank processes odd-numbered cache
  339. lines. The pointer P might be stored in an odd-numbered cache line, and the
  340. variable B might be stored in an even-numbered cache line. Then, if the
  341. even-numbered bank of the reading CPU's cache is extremely busy while the
  342. odd-numbered bank is idle, one can see the new value of the pointer P (&B),
  343. but the old value of the variable B (2).
  344. Another example of where data dependency barriers might by required is where a
  345. number is read from memory and then used to calculate the index for an array
  346. access:
  347. CPU 1 CPU 2
  348. =============== ===============
  349. { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
  350. M[1] = 4;
  351. <write barrier>
  352. P = 1
  353. Q = P;
  354. <data dependency barrier>
  355. D = M[Q];
  356. The data dependency barrier is very important to the RCU system, for example.
  357. See rcu_dereference() in include/linux/rcupdate.h. This permits the current
  358. target of an RCU'd pointer to be replaced with a new modified target, without
  359. the replacement target appearing to be incompletely initialised.
  360. See also the subsection on "Cache Coherency" for a more thorough example.
  361. CONTROL DEPENDENCIES
  362. --------------------
  363. A control dependency requires a full read memory barrier, not simply a data
  364. dependency barrier to make it work correctly. Consider the following bit of
  365. code:
  366. q = &a;
  367. if (p)
  368. q = &b;
  369. <data dependency barrier>
  370. x = *q;
  371. This will not have the desired effect because there is no actual data
  372. dependency, but rather a control dependency that the CPU may short-circuit by
  373. attempting to predict the outcome in advance. In such a case what's actually
  374. required is:
  375. q = &a;
  376. if (p)
  377. q = &b;
  378. <read barrier>
  379. x = *q;
  380. SMP BARRIER PAIRING
  381. -------------------
  382. When dealing with CPU-CPU interactions, certain types of memory barrier should
  383. always be paired. A lack of appropriate pairing is almost certainly an error.
  384. A write barrier should always be paired with a data dependency barrier or read
  385. barrier, though a general barrier would also be viable. Similarly a read
  386. barrier or a data dependency barrier should always be paired with at least an
  387. write barrier, though, again, a general barrier is viable:
  388. CPU 1 CPU 2
  389. =============== ===============
  390. a = 1;
  391. <write barrier>
  392. b = 2; x = b;
  393. <read barrier>
  394. y = a;
  395. Or:
  396. CPU 1 CPU 2
  397. =============== ===============================
  398. a = 1;
  399. <write barrier>
  400. b = &a; x = b;
  401. <data dependency barrier>
  402. y = *x;
  403. Basically, the read barrier always has to be there, even though it can be of
  404. the "weaker" type.
  405. [!] Note that the stores before the write barrier would normally be expected to
  406. match the loads after the read barrier or data dependency barrier, and vice
  407. versa:
  408. CPU 1 CPU 2
  409. =============== ===============
  410. a = 1; }---- --->{ v = c
  411. b = 2; } \ / { w = d
  412. <write barrier> \ <read barrier>
  413. c = 3; } / \ { x = a;
  414. d = 4; }---- --->{ y = b;
  415. EXAMPLES OF MEMORY BARRIER SEQUENCES
  416. ------------------------------------
  417. Firstly, write barriers act as a partial orderings on store operations.
  418. Consider the following sequence of events:
  419. CPU 1
  420. =======================
  421. STORE A = 1
  422. STORE B = 2
  423. STORE C = 3
  424. <write barrier>
  425. STORE D = 4
  426. STORE E = 5
  427. This sequence of events is committed to the memory coherence system in an order
  428. that the rest of the system might perceive as the unordered set of { STORE A,
  429. STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
  430. }:
  431. +-------+ : :
  432. | | +------+
  433. | |------>| C=3 | } /\
  434. | | : +------+ }----- \ -----> Events perceptible
  435. | | : | A=1 | } \/ to rest of system
  436. | | : +------+ }
  437. | CPU 1 | : | B=2 | }
  438. | | +------+ }
  439. | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
  440. | | +------+ } requires all stores prior to the
  441. | | : | E=5 | } barrier to be committed before
  442. | | : +------+ } further stores may be take place.
  443. | |------>| D=4 | }
  444. | | +------+
  445. +-------+ : :
  446. |
  447. | Sequence in which stores are committed to the
  448. | memory system by CPU 1
  449. V
  450. Secondly, data dependency barriers act as a partial orderings on data-dependent
  451. loads. Consider the following sequence of events:
  452. CPU 1 CPU 2
  453. ======================= =======================
  454. { B = 7; X = 9; Y = 8; C = &Y }
  455. STORE A = 1
  456. STORE B = 2
  457. <write barrier>
  458. STORE C = &B LOAD X
  459. STORE D = 4 LOAD C (gets &B)
  460. LOAD *C (reads B)
  461. Without intervention, CPU 2 may perceive the events on CPU 1 in some
  462. effectively random order, despite the write barrier issued by CPU 1:
  463. +-------+ : : : :
  464. | | +------+ +-------+ | Sequence of update
  465. | |------>| B=2 |----- --->| Y->8 | | of perception on
  466. | | : +------+ \ +-------+ | CPU 2
  467. | CPU 1 | : | A=1 | \ --->| C->&Y | V
  468. | | +------+ | +-------+
  469. | | wwwwwwwwwwwwwwww | : :
  470. | | +------+ | : :
  471. | | : | C=&B |--- | : : +-------+
  472. | | : +------+ \ | +-------+ | |
  473. | |------>| D=4 | ----------->| C->&B |------>| |
  474. | | +------+ | +-------+ | |
  475. +-------+ : : | : : | |
  476. | : : | |
  477. | : : | CPU 2 |
  478. | +-------+ | |
  479. Apparently incorrect ---> | | B->7 |------>| |
  480. perception of B (!) | +-------+ | |
  481. | : : | |
  482. | +-------+ | |
  483. The load of X holds ---> \ | X->9 |------>| |
  484. up the maintenance \ +-------+ | |
  485. of coherence of B ----->| B->2 | +-------+
  486. +-------+
  487. : :
  488. In the above example, CPU 2 perceives that B is 7, despite the load of *C
  489. (which would be B) coming after the LOAD of C.
  490. If, however, a data dependency barrier were to be placed between the load of C
  491. and the load of *C (ie: B) on CPU 2:
  492. CPU 1 CPU 2
  493. ======================= =======================
  494. { B = 7; X = 9; Y = 8; C = &Y }
  495. STORE A = 1
  496. STORE B = 2
  497. <write barrier>
  498. STORE C = &B LOAD X
  499. STORE D = 4 LOAD C (gets &B)
  500. <data dependency barrier>
  501. LOAD *C (reads B)
  502. then the following will occur:
  503. +-------+ : : : :
  504. | | +------+ +-------+
  505. | |------>| B=2 |----- --->| Y->8 |
  506. | | : +------+ \ +-------+
  507. | CPU 1 | : | A=1 | \ --->| C->&Y |
  508. | | +------+ | +-------+
  509. | | wwwwwwwwwwwwwwww | : :
  510. | | +------+ | : :
  511. | | : | C=&B |--- | : : +-------+
  512. | | : +------+ \ | +-------+ | |
  513. | |------>| D=4 | ----------->| C->&B |------>| |
  514. | | +------+ | +-------+ | |
  515. +-------+ : : | : : | |
  516. | : : | |
  517. | : : | CPU 2 |
  518. | +-------+ | |
  519. | | X->9 |------>| |
  520. | +-------+ | |
  521. Makes sure all effects ---> \ ddddddddddddddddd | |
  522. prior to the store of C \ +-------+ | |
  523. are perceptible to ----->| B->2 |------>| |
  524. subsequent loads +-------+ | |
  525. : : +-------+
  526. And thirdly, a read barrier acts as a partial order on loads. Consider the
  527. following sequence of events:
  528. CPU 1 CPU 2
  529. ======================= =======================
  530. { A = 0, B = 9 }
  531. STORE A=1
  532. <write barrier>
  533. STORE B=2
  534. LOAD B
  535. LOAD A
  536. Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
  537. some effectively random order, despite the write barrier issued by CPU 1:
  538. +-------+ : : : :
  539. | | +------+ +-------+
  540. | |------>| A=1 |------ --->| A->0 |
  541. | | +------+ \ +-------+
  542. | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
  543. | | +------+ | +-------+
  544. | |------>| B=2 |--- | : :
  545. | | +------+ \ | : : +-------+
  546. +-------+ : : \ | +-------+ | |
  547. ---------->| B->2 |------>| |
  548. | +-------+ | CPU 2 |
  549. | | A->0 |------>| |
  550. | +-------+ | |
  551. | : : +-------+
  552. \ : :
  553. \ +-------+
  554. ---->| A->1 |
  555. +-------+
  556. : :
  557. If, however, a read barrier were to be placed between the load of B and the
  558. load of A on CPU 2:
  559. CPU 1 CPU 2
  560. ======================= =======================
  561. { A = 0, B = 9 }
  562. STORE A=1
  563. <write barrier>
  564. STORE B=2
  565. LOAD B
  566. <read barrier>
  567. LOAD A
  568. then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
  569. 2:
  570. +-------+ : : : :
  571. | | +------+ +-------+
  572. | |------>| A=1 |------ --->| A->0 |
  573. | | +------+ \ +-------+
  574. | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
  575. | | +------+ | +-------+
  576. | |------>| B=2 |--- | : :
  577. | | +------+ \ | : : +-------+
  578. +-------+ : : \ | +-------+ | |
  579. ---------->| B->2 |------>| |
  580. | +-------+ | CPU 2 |
  581. | : : | |
  582. | : : | |
  583. At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
  584. barrier causes all effects \ +-------+ | |
  585. prior to the storage of B ---->| A->1 |------>| |
  586. to be perceptible to CPU 2 +-------+ | |
  587. : : +-------+
  588. To illustrate this more completely, consider what could happen if the code
  589. contained a load of A either side of the read barrier:
  590. CPU 1 CPU 2
  591. ======================= =======================
  592. { A = 0, B = 9 }
  593. STORE A=1
  594. <write barrier>
  595. STORE B=2
  596. LOAD B
  597. LOAD A [first load of A]
  598. <read barrier>
  599. LOAD A [second load of A]
  600. Even though the two loads of A both occur after the load of B, they may both
  601. come up with different values:
  602. +-------+ : : : :
  603. | | +------+ +-------+
  604. | |------>| A=1 |------ --->| A->0 |
  605. | | +------+ \ +-------+
  606. | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
  607. | | +------+ | +-------+
  608. | |------>| B=2 |--- | : :
  609. | | +------+ \ | : : +-------+
  610. +-------+ : : \ | +-------+ | |
  611. ---------->| B->2 |------>| |
  612. | +-------+ | CPU 2 |
  613. | : : | |
  614. | : : | |
  615. | +-------+ | |
  616. | | A->0 |------>| 1st |
  617. | +-------+ | |
  618. At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
  619. barrier causes all effects \ +-------+ | |
  620. prior to the storage of B ---->| A->1 |------>| 2nd |
  621. to be perceptible to CPU 2 +-------+ | |
  622. : : +-------+
  623. But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
  624. before the read barrier completes anyway:
  625. +-------+ : : : :
  626. | | +------+ +-------+
  627. | |------>| A=1 |------ --->| A->0 |
  628. | | +------+ \ +-------+
  629. | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
  630. | | +------+ | +-------+
  631. | |------>| B=2 |--- | : :
  632. | | +------+ \ | : : +-------+
  633. +-------+ : : \ | +-------+ | |
  634. ---------->| B->2 |------>| |
  635. | +-------+ | CPU 2 |
  636. | : : | |
  637. \ : : | |
  638. \ +-------+ | |
  639. ---->| A->1 |------>| 1st |
  640. +-------+ | |
  641. rrrrrrrrrrrrrrrrr | |
  642. +-------+ | |
  643. | A->1 |------>| 2nd |
  644. +-------+ | |
  645. : : +-------+
  646. The guarantee is that the second load will always come up with A == 1 if the
  647. load of B came up with B == 2. No such guarantee exists for the first load of
  648. A; that may come up with either A == 0 or A == 1.
  649. READ MEMORY BARRIERS VS LOAD SPECULATION
  650. ----------------------------------------
  651. Many CPUs speculate with loads: that is they see that they will need to load an
  652. item from memory, and they find a time where they're not using the bus for any
  653. other loads, and so do the load in advance - even though they haven't actually
  654. got to that point in the instruction execution flow yet. This permits the
  655. actual load instruction to potentially complete immediately because the CPU
  656. already has the value to hand.
  657. It may turn out that the CPU didn't actually need the value - perhaps because a
  658. branch circumvented the load - in which case it can discard the value or just
  659. cache it for later use.
  660. Consider:
  661. CPU 1 CPU 2
  662. ======================= =======================
  663. LOAD B
  664. DIVIDE } Divide instructions generally
  665. DIVIDE } take a long time to perform
  666. LOAD A
  667. Which might appear as this:
  668. : : +-------+
  669. +-------+ | |
  670. --->| B->2 |------>| |
  671. +-------+ | CPU 2 |
  672. : :DIVIDE | |
  673. +-------+ | |
  674. The CPU being busy doing a ---> --->| A->0 |~~~~ | |
  675. division speculates on the +-------+ ~ | |
  676. LOAD of A : : ~ | |
  677. : :DIVIDE | |
  678. : : ~ | |
  679. Once the divisions are complete --> : : ~-->| |
  680. the CPU can then perform the : : | |
  681. LOAD with immediate effect : : +-------+
  682. Placing a read barrier or a data dependency barrier just before the second
  683. load:
  684. CPU 1 CPU 2
  685. ======================= =======================
  686. LOAD B
  687. DIVIDE
  688. DIVIDE
  689. <read barrier>
  690. LOAD A
  691. will force any value speculatively obtained to be reconsidered to an extent
  692. dependent on the type of barrier used. If there was no change made to the
  693. speculated memory location, then the speculated value will just be used:
  694. : : +-------+
  695. +-------+ | |
  696. --->| B->2 |------>| |
  697. +-------+ | CPU 2 |
  698. : :DIVIDE | |
  699. +-------+ | |
  700. The CPU being busy doing a ---> --->| A->0 |~~~~ | |
  701. division speculates on the +-------+ ~ | |
  702. LOAD of A : : ~ | |
  703. : :DIVIDE | |
  704. : : ~ | |
  705. : : ~ | |
  706. rrrrrrrrrrrrrrrr~ | |
  707. : : ~ | |
  708. : : ~-->| |
  709. : : | |
  710. : : +-------+
  711. but if there was an update or an invalidation from another CPU pending, then
  712. the speculation will be cancelled and the value reloaded:
  713. : : +-------+
  714. +-------+ | |
  715. --->| B->2 |------>| |
  716. +-------+ | CPU 2 |
  717. : :DIVIDE | |
  718. +-------+ | |
  719. The CPU being busy doing a ---> --->| A->0 |~~~~ | |
  720. division speculates on the +-------+ ~ | |
  721. LOAD of A : : ~ | |
  722. : :DIVIDE | |
  723. : : ~ | |
  724. : : ~ | |
  725. rrrrrrrrrrrrrrrrr | |
  726. +-------+ | |
  727. The speculation is discarded ---> --->| A->1 |------>| |
  728. and an updated value is +-------+ | |
  729. retrieved : : +-------+
  730. ========================
  731. EXPLICIT KERNEL BARRIERS
  732. ========================
  733. The Linux kernel has a variety of different barriers that act at different
  734. levels:
  735. (*) Compiler barrier.
  736. (*) CPU memory barriers.
  737. (*) MMIO write barrier.
  738. COMPILER BARRIER
  739. ----------------
  740. The Linux kernel has an explicit compiler barrier function that prevents the
  741. compiler from moving the memory accesses either side of it to the other side:
  742. barrier();
  743. This a general barrier - lesser varieties of compiler barrier do not exist.
  744. The compiler barrier has no direct effect on the CPU, which may then reorder
  745. things however it wishes.
  746. CPU MEMORY BARRIERS
  747. -------------------
  748. The Linux kernel has eight basic CPU memory barriers:
  749. TYPE MANDATORY SMP CONDITIONAL
  750. =============== ======================= ===========================
  751. GENERAL mb() smp_mb()
  752. WRITE wmb() smp_wmb()
  753. READ rmb() smp_rmb()
  754. DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
  755. All CPU memory barriers unconditionally imply compiler barriers.
  756. SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
  757. systems because it is assumed that a CPU will be appear to be self-consistent,
  758. and will order overlapping accesses correctly with respect to itself.
  759. [!] Note that SMP memory barriers _must_ be used to control the ordering of
  760. references to shared memory on SMP systems, though the use of locking instead
  761. is sufficient.
  762. Mandatory barriers should not be used to control SMP effects, since mandatory
  763. barriers unnecessarily impose overhead on UP systems. They may, however, be
  764. used to control MMIO effects on accesses through relaxed memory I/O windows.
  765. These are required even on non-SMP systems as they affect the order in which
  766. memory operations appear to a device by prohibiting both the compiler and the
  767. CPU from reordering them.
  768. There are some more advanced barrier functions:
  769. (*) set_mb(var, value)
  770. This assigns the value to the variable and then inserts a full memory
  771. barrier after it, depending on the function. It isn't guaranteed to
  772. insert anything more than a compiler barrier in a UP compilation.
  773. (*) smp_mb__before_atomic_dec();
  774. (*) smp_mb__after_atomic_dec();
  775. (*) smp_mb__before_atomic_inc();
  776. (*) smp_mb__after_atomic_inc();
  777. These are for use with atomic add, subtract, increment and decrement
  778. functions that don't return a value, especially when used for reference
  779. counting. These functions do not imply memory barriers.
  780. As an example, consider a piece of code that marks an object as being dead
  781. and then decrements the object's reference count:
  782. obj->dead = 1;
  783. smp_mb__before_atomic_dec();
  784. atomic_dec(&obj->ref_count);
  785. This makes sure that the death mark on the object is perceived to be set
  786. *before* the reference counter is decremented.
  787. See Documentation/atomic_ops.txt for more information. See the "Atomic
  788. operations" subsection for information on where to use these.
  789. (*) smp_mb__before_clear_bit(void);
  790. (*) smp_mb__after_clear_bit(void);
  791. These are for use similar to the atomic inc/dec barriers. These are
  792. typically used for bitwise unlocking operations, so care must be taken as
  793. there are no implicit memory barriers here either.
  794. Consider implementing an unlock operation of some nature by clearing a
  795. locking bit. The clear_bit() would then need to be barriered like this:
  796. smp_mb__before_clear_bit();
  797. clear_bit( ... );
  798. This prevents memory operations before the clear leaking to after it. See
  799. the subsection on "Locking Functions" with reference to UNLOCK operation
  800. implications.
  801. See Documentation/atomic_ops.txt for more information. See the "Atomic
  802. operations" subsection for information on where to use these.
  803. MMIO WRITE BARRIER
  804. ------------------
  805. The Linux kernel also has a special barrier for use with memory-mapped I/O
  806. writes:
  807. mmiowb();
  808. This is a variation on the mandatory write barrier that causes writes to weakly
  809. ordered I/O regions to be partially ordered. Its effects may go beyond the
  810. CPU->Hardware interface and actually affect the hardware at some level.
  811. See the subsection "Locks vs I/O accesses" for more information.
  812. ===============================
  813. IMPLICIT KERNEL MEMORY BARRIERS
  814. ===============================
  815. Some of the other functions in the linux kernel imply memory barriers, amongst
  816. which are locking and scheduling functions.
  817. This specification is a _minimum_ guarantee; any particular architecture may
  818. provide more substantial guarantees, but these may not be relied upon outside
  819. of arch specific code.
  820. LOCKING FUNCTIONS
  821. -----------------
  822. The Linux kernel has a number of locking constructs:
  823. (*) spin locks
  824. (*) R/W spin locks
  825. (*) mutexes
  826. (*) semaphores
  827. (*) R/W semaphores
  828. (*) RCU
  829. In all cases there are variants on "LOCK" operations and "UNLOCK" operations
  830. for each construct. These operations all imply certain barriers:
  831. (1) LOCK operation implication:
  832. Memory operations issued after the LOCK will be completed after the LOCK
  833. operation has completed.
  834. Memory operations issued before the LOCK may be completed after the LOCK
  835. operation has completed.
  836. (2) UNLOCK operation implication:
  837. Memory operations issued before the UNLOCK will be completed before the
  838. UNLOCK operation has completed.
  839. Memory operations issued after the UNLOCK may be completed before the
  840. UNLOCK operation has completed.
  841. (3) LOCK vs LOCK implication:
  842. All LOCK operations issued before another LOCK operation will be completed
  843. before that LOCK operation.
  844. (4) LOCK vs UNLOCK implication:
  845. All LOCK operations issued before an UNLOCK operation will be completed
  846. before the UNLOCK operation.
  847. All UNLOCK operations issued before a LOCK operation will be completed
  848. before the LOCK operation.
  849. (5) Failed conditional LOCK implication:
  850. Certain variants of the LOCK operation may fail, either due to being
  851. unable to get the lock immediately, or due to receiving an unblocked
  852. signal whilst asleep waiting for the lock to become available. Failed
  853. locks do not imply any sort of barrier.
  854. Therefore, from (1), (2) and (4) an UNLOCK followed by an unconditional LOCK is
  855. equivalent to a full barrier, but a LOCK followed by an UNLOCK is not.
  856. [!] Note: one of the consequence of LOCKs and UNLOCKs being only one-way
  857. barriers is that the effects instructions outside of a critical section may
  858. seep into the inside of the critical section.
  859. A LOCK followed by an UNLOCK may not be assumed to be full memory barrier
  860. because it is possible for an access preceding the LOCK to happen after the
  861. LOCK, and an access following the UNLOCK to happen before the UNLOCK, and the
  862. two accesses can themselves then cross:
  863. *A = a;
  864. LOCK
  865. UNLOCK
  866. *B = b;
  867. may occur as:
  868. LOCK, STORE *B, STORE *A, UNLOCK
  869. Locks and semaphores may not provide any guarantee of ordering on UP compiled
  870. systems, and so cannot be counted on in such a situation to actually achieve
  871. anything at all - especially with respect to I/O accesses - unless combined
  872. with interrupt disabling operations.
  873. See also the section on "Inter-CPU locking barrier effects".
  874. As an example, consider the following:
  875. *A = a;
  876. *B = b;
  877. LOCK
  878. *C = c;
  879. *D = d;
  880. UNLOCK
  881. *E = e;
  882. *F = f;
  883. The following sequence of events is acceptable:
  884. LOCK, {*F,*A}, *E, {*C,*D}, *B, UNLOCK
  885. [+] Note that {*F,*A} indicates a combined access.
  886. But none of the following are:
  887. {*F,*A}, *B, LOCK, *C, *D, UNLOCK, *E
  888. *A, *B, *C, LOCK, *D, UNLOCK, *E, *F
  889. *A, *B, LOCK, *C, UNLOCK, *D, *E, *F
  890. *B, LOCK, *C, *D, UNLOCK, {*F,*A}, *E
  891. INTERRUPT DISABLING FUNCTIONS
  892. -----------------------------
  893. Functions that disable interrupts (LOCK equivalent) and enable interrupts
  894. (UNLOCK equivalent) will act as compiler barriers only. So if memory or I/O
  895. barriers are required in such a situation, they must be provided from some
  896. other means.
  897. MISCELLANEOUS FUNCTIONS
  898. -----------------------
  899. Other functions that imply barriers:
  900. (*) schedule() and similar imply full memory barriers.
  901. =================================
  902. INTER-CPU LOCKING BARRIER EFFECTS
  903. =================================
  904. On SMP systems locking primitives give a more substantial form of barrier: one
  905. that does affect memory access ordering on other CPUs, within the context of
  906. conflict on any particular lock.
  907. LOCKS VS MEMORY ACCESSES
  908. ------------------------
  909. Consider the following: the system has a pair of spinlocks (M) and (Q), and
  910. three CPUs; then should the following sequence of events occur:
  911. CPU 1 CPU 2
  912. =============================== ===============================
  913. *A = a; *E = e;
  914. LOCK M LOCK Q
  915. *B = b; *F = f;
  916. *C = c; *G = g;
  917. UNLOCK M UNLOCK Q
  918. *D = d; *H = h;
  919. Then there is no guarantee as to what order CPU #3 will see the accesses to *A
  920. through *H occur in, other than the constraints imposed by the separate locks
  921. on the separate CPUs. It might, for example, see:
  922. *E, LOCK M, LOCK Q, *G, *C, *F, *A, *B, UNLOCK Q, *D, *H, UNLOCK M
  923. But it won't see any of:
  924. *B, *C or *D preceding LOCK M
  925. *A, *B or *C following UNLOCK M
  926. *F, *G or *H preceding LOCK Q
  927. *E, *F or *G following UNLOCK Q
  928. However, if the following occurs:
  929. CPU 1 CPU 2
  930. =============================== ===============================
  931. *A = a;
  932. LOCK M [1]
  933. *B = b;
  934. *C = c;
  935. UNLOCK M [1]
  936. *D = d; *E = e;
  937. LOCK M [2]
  938. *F = f;
  939. *G = g;
  940. UNLOCK M [2]
  941. *H = h;
  942. CPU #3 might see:
  943. *E, LOCK M [1], *C, *B, *A, UNLOCK M [1],
  944. LOCK M [2], *H, *F, *G, UNLOCK M [2], *D
  945. But assuming CPU #1 gets the lock first, it won't see any of:
  946. *B, *C, *D, *F, *G or *H preceding LOCK M [1]
  947. *A, *B or *C following UNLOCK M [1]
  948. *F, *G or *H preceding LOCK M [2]
  949. *A, *B, *C, *E, *F or *G following UNLOCK M [2]
  950. LOCKS VS I/O ACCESSES
  951. ---------------------
  952. Under certain circumstances (especially involving NUMA), I/O accesses within
  953. two spinlocked sections on two different CPUs may be seen as interleaved by the
  954. PCI bridge, because the PCI bridge does not necessarily participate in the
  955. cache-coherence protocol, and is therefore incapable of issuing the required
  956. read memory barriers.
  957. For example:
  958. CPU 1 CPU 2
  959. =============================== ===============================
  960. spin_lock(Q)
  961. writel(0, ADDR)
  962. writel(1, DATA);
  963. spin_unlock(Q);
  964. spin_lock(Q);
  965. writel(4, ADDR);
  966. writel(5, DATA);
  967. spin_unlock(Q);
  968. may be seen by the PCI bridge as follows:
  969. STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
  970. which would probably cause the hardware to malfunction.
  971. What is necessary here is to intervene with an mmiowb() before dropping the
  972. spinlock, for example:
  973. CPU 1 CPU 2
  974. =============================== ===============================
  975. spin_lock(Q)
  976. writel(0, ADDR)
  977. writel(1, DATA);
  978. mmiowb();
  979. spin_unlock(Q);
  980. spin_lock(Q);
  981. writel(4, ADDR);
  982. writel(5, DATA);
  983. mmiowb();
  984. spin_unlock(Q);
  985. this will ensure that the two stores issued on CPU #1 appear at the PCI bridge
  986. before either of the stores issued on CPU #2.
  987. Furthermore, following a store by a load to the same device obviates the need
  988. for an mmiowb(), because the load forces the store to complete before the load
  989. is performed:
  990. CPU 1 CPU 2
  991. =============================== ===============================
  992. spin_lock(Q)
  993. writel(0, ADDR)
  994. a = readl(DATA);
  995. spin_unlock(Q);
  996. spin_lock(Q);
  997. writel(4, ADDR);
  998. b = readl(DATA);
  999. spin_unlock(Q);
  1000. See Documentation/DocBook/deviceiobook.tmpl for more information.
  1001. =================================
  1002. WHERE ARE MEMORY BARRIERS NEEDED?
  1003. =================================
  1004. Under normal operation, memory operation reordering is generally not going to
  1005. be a problem as a single-threaded linear piece of code will still appear to
  1006. work correctly, even if it's in an SMP kernel. There are, however, three
  1007. circumstances in which reordering definitely _could_ be a problem:
  1008. (*) Interprocessor interaction.
  1009. (*) Atomic operations.
  1010. (*) Accessing devices (I/O).
  1011. (*) Interrupts.
  1012. INTERPROCESSOR INTERACTION
  1013. --------------------------
  1014. When there's a system with more than one processor, more than one CPU in the
  1015. system may be working on the same data set at the same time. This can cause
  1016. synchronisation problems, and the usual way of dealing with them is to use
  1017. locks. Locks, however, are quite expensive, and so it may be preferable to
  1018. operate without the use of a lock if at all possible. In such a case
  1019. operations that affect both CPUs may have to be carefully ordered to prevent
  1020. a malfunction.
  1021. Consider, for example, the R/W semaphore slow path. Here a waiting process is
  1022. queued on the semaphore, by virtue of it having a piece of its stack linked to
  1023. the semaphore's list of waiting processes:
  1024. struct rw_semaphore {
  1025. ...
  1026. spinlock_t lock;
  1027. struct list_head waiters;
  1028. };
  1029. struct rwsem_waiter {
  1030. struct list_head list;
  1031. struct task_struct *task;
  1032. };
  1033. To wake up a particular waiter, the up_read() or up_write() functions have to:
  1034. (1) read the next pointer from this waiter's record to know as to where the
  1035. next waiter record is;
  1036. (4) read the pointer to the waiter's task structure;
  1037. (3) clear the task pointer to tell the waiter it has been given the semaphore;
  1038. (4) call wake_up_process() on the task; and
  1039. (5) release the reference held on the waiter's task struct.
  1040. In otherwords, it has to perform this sequence of events:
  1041. LOAD waiter->list.next;
  1042. LOAD waiter->task;
  1043. STORE waiter->task;
  1044. CALL wakeup
  1045. RELEASE task
  1046. and if any of these steps occur out of order, then the whole thing may
  1047. malfunction.
  1048. Once it has queued itself and dropped the semaphore lock, the waiter does not
  1049. get the lock again; it instead just waits for its task pointer to be cleared
  1050. before proceeding. Since the record is on the waiter's stack, this means that
  1051. if the task pointer is cleared _before_ the next pointer in the list is read,
  1052. another CPU might start processing the waiter and might clobber the waiter's
  1053. stack before the up*() function has a chance to read the next pointer.
  1054. Consider then what might happen to the above sequence of events:
  1055. CPU 1 CPU 2
  1056. =============================== ===============================
  1057. down_xxx()
  1058. Queue waiter
  1059. Sleep
  1060. up_yyy()
  1061. LOAD waiter->task;
  1062. STORE waiter->task;
  1063. Woken up by other event
  1064. <preempt>
  1065. Resume processing
  1066. down_xxx() returns
  1067. call foo()
  1068. foo() clobbers *waiter
  1069. </preempt>
  1070. LOAD waiter->list.next;
  1071. --- OOPS ---
  1072. This could be dealt with using the semaphore lock, but then the down_xxx()
  1073. function has to needlessly get the spinlock again after being woken up.
  1074. The way to deal with this is to insert a general SMP memory barrier:
  1075. LOAD waiter->list.next;
  1076. LOAD waiter->task;
  1077. smp_mb();
  1078. STORE waiter->task;
  1079. CALL wakeup
  1080. RELEASE task
  1081. In this case, the barrier makes a guarantee that all memory accesses before the
  1082. barrier will appear to happen before all the memory accesses after the barrier
  1083. with respect to the other CPUs on the system. It does _not_ guarantee that all
  1084. the memory accesses before the barrier will be complete by the time the barrier
  1085. instruction itself is complete.
  1086. On a UP system - where this wouldn't be a problem - the smp_mb() is just a
  1087. compiler barrier, thus making sure the compiler emits the instructions in the
  1088. right order without actually intervening in the CPU. Since there's only one
  1089. CPU, that CPU's dependency ordering logic will take care of everything else.
  1090. ATOMIC OPERATIONS
  1091. -----------------
  1092. Whilst they are technically interprocessor interaction considerations, atomic
  1093. operations are noted specially as some of them imply full memory barriers and
  1094. some don't, but they're very heavily relied on as a group throughout the
  1095. kernel.
  1096. Any atomic operation that modifies some state in memory and returns information
  1097. about the state (old or new) implies an SMP-conditional general memory barrier
  1098. (smp_mb()) on each side of the actual operation. These include:
  1099. xchg();
  1100. cmpxchg();
  1101. atomic_cmpxchg();
  1102. atomic_inc_return();
  1103. atomic_dec_return();
  1104. atomic_add_return();
  1105. atomic_sub_return();
  1106. atomic_inc_and_test();
  1107. atomic_dec_and_test();
  1108. atomic_sub_and_test();
  1109. atomic_add_negative();
  1110. atomic_add_unless();
  1111. test_and_set_bit();
  1112. test_and_clear_bit();
  1113. test_and_change_bit();
  1114. These are used for such things as implementing LOCK-class and UNLOCK-class
  1115. operations and adjusting reference counters towards object destruction, and as
  1116. such the implicit memory barrier effects are necessary.
  1117. The following operation are potential problems as they do _not_ imply memory
  1118. barriers, but might be used for implementing such things as UNLOCK-class
  1119. operations:
  1120. atomic_set();
  1121. set_bit();
  1122. clear_bit();
  1123. change_bit();
  1124. With these the appropriate explicit memory barrier should be used if necessary
  1125. (smp_mb__before_clear_bit() for instance).
  1126. The following also do _not_ imply memory barriers, and so may require explicit
  1127. memory barriers under some circumstances (smp_mb__before_atomic_dec() for
  1128. instance)):
  1129. atomic_add();
  1130. atomic_sub();
  1131. atomic_inc();
  1132. atomic_dec();
  1133. If they're used for statistics generation, then they probably don't need memory
  1134. barriers, unless there's a coupling between statistical data.
  1135. If they're used for reference counting on an object to control its lifetime,
  1136. they probably don't need memory barriers because either the reference count
  1137. will be adjusted inside a locked section, or the caller will already hold
  1138. sufficient references to make the lock, and thus a memory barrier unnecessary.
  1139. If they're used for constructing a lock of some description, then they probably
  1140. do need memory barriers as a lock primitive generally has to do things in a
  1141. specific order.
  1142. Basically, each usage case has to be carefully considered as to whether memory
  1143. barriers are needed or not.
  1144. [!] Note that special memory barrier primitives are available for these
  1145. situations because on some CPUs the atomic instructions used imply full memory
  1146. barriers, and so barrier instructions are superfluous in conjunction with them,
  1147. and in such cases the special barrier primitives will be no-ops.
  1148. See Documentation/atomic_ops.txt for more information.
  1149. ACCESSING DEVICES
  1150. -----------------
  1151. Many devices can be memory mapped, and so appear to the CPU as if they're just
  1152. a set of memory locations. To control such a device, the driver usually has to
  1153. make the right memory accesses in exactly the right order.
  1154. However, having a clever CPU or a clever compiler creates a potential problem
  1155. in that the carefully sequenced accesses in the driver code won't reach the
  1156. device in the requisite order if the CPU or the compiler thinks it is more
  1157. efficient to reorder, combine or merge accesses - something that would cause
  1158. the device to malfunction.
  1159. Inside of the Linux kernel, I/O should be done through the appropriate accessor
  1160. routines - such as inb() or writel() - which know how to make such accesses
  1161. appropriately sequential. Whilst this, for the most part, renders the explicit
  1162. use of memory barriers unnecessary, there are a couple of situations where they
  1163. might be needed:
  1164. (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
  1165. so for _all_ general drivers locks should be used and mmiowb() must be
  1166. issued prior to unlocking the critical section.
  1167. (2) If the accessor functions are used to refer to an I/O memory window with
  1168. relaxed memory access properties, then _mandatory_ memory barriers are
  1169. required to enforce ordering.
  1170. See Documentation/DocBook/deviceiobook.tmpl for more information.
  1171. INTERRUPTS
  1172. ----------
  1173. A driver may be interrupted by its own interrupt service routine, and thus the
  1174. two parts of the driver may interfere with each other's attempts to control or
  1175. access the device.
  1176. This may be alleviated - at least in part - by disabling local interrupts (a
  1177. form of locking), such that the critical operations are all contained within
  1178. the interrupt-disabled section in the driver. Whilst the driver's interrupt
  1179. routine is executing, the driver's core may not run on the same CPU, and its
  1180. interrupt is not permitted to happen again until the current interrupt has been
  1181. handled, thus the interrupt handler does not need to lock against that.
  1182. However, consider a driver that was talking to an ethernet card that sports an
  1183. address register and a data register. If that driver's core talks to the card
  1184. under interrupt-disablement and then the driver's interrupt handler is invoked:
  1185. LOCAL IRQ DISABLE
  1186. writew(ADDR, 3);
  1187. writew(DATA, y);
  1188. LOCAL IRQ ENABLE
  1189. <interrupt>
  1190. writew(ADDR, 4);
  1191. q = readw(DATA);
  1192. </interrupt>
  1193. The store to the data register might happen after the second store to the
  1194. address register if ordering rules are sufficiently relaxed:
  1195. STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
  1196. If ordering rules are relaxed, it must be assumed that accesses done inside an
  1197. interrupt disabled section may leak outside of it and may interleave with
  1198. accesses performed in an interrupt - and vice versa - unless implicit or
  1199. explicit barriers are used.
  1200. Normally this won't be a problem because the I/O accesses done inside such
  1201. sections will include synchronous load operations on strictly ordered I/O
  1202. registers that form implicit I/O barriers. If this isn't sufficient then an
  1203. mmiowb() may need to be used explicitly.
  1204. A similar situation may occur between an interrupt routine and two routines
  1205. running on separate CPUs that communicate with each other. If such a case is
  1206. likely, then interrupt-disabling locks should be used to guarantee ordering.
  1207. ==========================
  1208. KERNEL I/O BARRIER EFFECTS
  1209. ==========================
  1210. When accessing I/O memory, drivers should use the appropriate accessor
  1211. functions:
  1212. (*) inX(), outX():
  1213. These are intended to talk to I/O space rather than memory space, but
  1214. that's primarily a CPU-specific concept. The i386 and x86_64 processors do
  1215. indeed have special I/O space access cycles and instructions, but many
  1216. CPUs don't have such a concept.
  1217. The PCI bus, amongst others, defines an I/O space concept - which on such
  1218. CPUs as i386 and x86_64 cpus readily maps to the CPU's concept of I/O
  1219. space. However, it may also be mapped as a virtual I/O space in the CPU's
  1220. memory map, particularly on those CPUs that don't support alternate I/O
  1221. spaces.
  1222. Accesses to this space may be fully synchronous (as on i386), but
  1223. intermediary bridges (such as the PCI host bridge) may not fully honour
  1224. that.
  1225. They are guaranteed to be fully ordered with respect to each other.
  1226. They are not guaranteed to be fully ordered with respect to other types of
  1227. memory and I/O operation.
  1228. (*) readX(), writeX():
  1229. Whether these are guaranteed to be fully ordered and uncombined with
  1230. respect to each other on the issuing CPU depends on the characteristics
  1231. defined for the memory window through which they're accessing. On later
  1232. i386 architecture machines, for example, this is controlled by way of the
  1233. MTRR registers.
  1234. Ordinarily, these will be guaranteed to be fully ordered and uncombined,,
  1235. provided they're not accessing a prefetchable device.
  1236. However, intermediary hardware (such as a PCI bridge) may indulge in
  1237. deferral if it so wishes; to flush a store, a load from the same location
  1238. is preferred[*], but a load from the same device or from configuration
  1239. space should suffice for PCI.
  1240. [*] NOTE! attempting to load from the same location as was written to may
  1241. cause a malfunction - consider the 16550 Rx/Tx serial registers for
  1242. example.
  1243. Used with prefetchable I/O memory, an mmiowb() barrier may be required to
  1244. force stores to be ordered.
  1245. Please refer to the PCI specification for more information on interactions
  1246. between PCI transactions.
  1247. (*) readX_relaxed()
  1248. These are similar to readX(), but are not guaranteed to be ordered in any
  1249. way. Be aware that there is no I/O read barrier available.
  1250. (*) ioreadX(), iowriteX()
  1251. These will perform as appropriate for the type of access they're actually
  1252. doing, be it inX()/outX() or readX()/writeX().
  1253. ========================================
  1254. ASSUMED MINIMUM EXECUTION ORDERING MODEL
  1255. ========================================
  1256. It has to be assumed that the conceptual CPU is weakly-ordered but that it will
  1257. maintain the appearance of program causality with respect to itself. Some CPUs
  1258. (such as i386 or x86_64) are more constrained than others (such as powerpc or
  1259. frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
  1260. of arch-specific code.
  1261. This means that it must be considered that the CPU will execute its instruction
  1262. stream in any order it feels like - or even in parallel - provided that if an
  1263. instruction in the stream depends on the an earlier instruction, then that
  1264. earlier instruction must be sufficiently complete[*] before the later
  1265. instruction may proceed; in other words: provided that the appearance of
  1266. causality is maintained.
  1267. [*] Some instructions have more than one effect - such as changing the
  1268. condition codes, changing registers or changing memory - and different
  1269. instructions may depend on different effects.
  1270. A CPU may also discard any instruction sequence that winds up having no
  1271. ultimate effect. For example, if two adjacent instructions both load an
  1272. immediate value into the same register, the first may be discarded.
  1273. Similarly, it has to be assumed that compiler might reorder the instruction
  1274. stream in any way it sees fit, again provided the appearance of causality is
  1275. maintained.
  1276. ============================
  1277. THE EFFECTS OF THE CPU CACHE
  1278. ============================
  1279. The way cached memory operations are perceived across the system is affected to
  1280. a certain extent by the caches that lie between CPUs and memory, and by the
  1281. memory coherence system that maintains the consistency of state in the system.
  1282. As far as the way a CPU interacts with another part of the system through the
  1283. caches goes, the memory system has to include the CPU's caches, and memory
  1284. barriers for the most part act at the interface between the CPU and its cache
  1285. (memory barriers logically act on the dotted line in the following diagram):
  1286. <--- CPU ---> : <----------- Memory ----------->
  1287. :
  1288. +--------+ +--------+ : +--------+ +-----------+
  1289. | | | | : | | | | +--------+
  1290. | CPU | | Memory | : | CPU | | | | |
  1291. | Core |--->| Access |----->| Cache |<-->| | | |
  1292. | | | Queue | : | | | |--->| Memory |
  1293. | | | | : | | | | | |
  1294. +--------+ +--------+ : +--------+ | | | |
  1295. : | Cache | +--------+
  1296. : | Coherency |
  1297. : | Mechanism | +--------+
  1298. +--------+ +--------+ : +--------+ | | | |
  1299. | | | | : | | | | | |
  1300. | CPU | | Memory | : | CPU | | |--->| Device |
  1301. | Core |--->| Access |----->| Cache |<-->| | | |
  1302. | | | Queue | : | | | | | |
  1303. | | | | : | | | | +--------+
  1304. +--------+ +--------+ : +--------+ +-----------+
  1305. :
  1306. :
  1307. Although any particular load or store may not actually appear outside of the
  1308. CPU that issued it since it may have been satisfied within the CPU's own cache,
  1309. it will still appear as if the full memory access had taken place as far as the
  1310. other CPUs are concerned since the cache coherency mechanisms will migrate the
  1311. cacheline over to the accessing CPU and propagate the effects upon conflict.
  1312. The CPU core may execute instructions in any order it deems fit, provided the
  1313. expected program causality appears to be maintained. Some of the instructions
  1314. generate load and store operations which then go into the queue of memory
  1315. accesses to be performed. The core may place these in the queue in any order
  1316. it wishes, and continue execution until it is forced to wait for an instruction
  1317. to complete.
  1318. What memory barriers are concerned with is controlling the order in which
  1319. accesses cross from the CPU side of things to the memory side of things, and
  1320. the order in which the effects are perceived to happen by the other observers
  1321. in the system.
  1322. [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
  1323. their own loads and stores as if they had happened in program order.
  1324. [!] MMIO or other device accesses may bypass the cache system. This depends on
  1325. the properties of the memory window through which devices are accessed and/or
  1326. the use of any special device communication instructions the CPU may have.
  1327. CACHE COHERENCY
  1328. ---------------
  1329. Life isn't quite as simple as it may appear above, however: for while the
  1330. caches are expected to be coherent, there's no guarantee that that coherency
  1331. will be ordered. This means that whilst changes made on one CPU will
  1332. eventually become visible on all CPUs, there's no guarantee that they will
  1333. become apparent in the same order on those other CPUs.
  1334. Consider dealing with a system that has pair of CPUs (1 & 2), each of which has
  1335. a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
  1336. :
  1337. : +--------+
  1338. : +---------+ | |
  1339. +--------+ : +--->| Cache A |<------->| |
  1340. | | : | +---------+ | |
  1341. | CPU 1 |<---+ | |
  1342. | | : | +---------+ | |
  1343. +--------+ : +--->| Cache B |<------->| |
  1344. : +---------+ | |
  1345. : | Memory |
  1346. : +---------+ | System |
  1347. +--------+ : +--->| Cache C |<------->| |
  1348. | | : | +---------+ | |
  1349. | CPU 2 |<---+ | |
  1350. | | : | +---------+ | |
  1351. +--------+ : +--->| Cache D |<------->| |
  1352. : +---------+ | |
  1353. : +--------+
  1354. :
  1355. Imagine the system has the following properties:
  1356. (*) an odd-numbered cache line may be in cache A, cache C or it may still be
  1357. resident in memory;
  1358. (*) an even-numbered cache line may be in cache B, cache D or it may still be
  1359. resident in memory;
  1360. (*) whilst the CPU core is interrogating one cache, the other cache may be
  1361. making use of the bus to access the rest of the system - perhaps to
  1362. displace a dirty cacheline or to do a speculative load;
  1363. (*) each cache has a queue of operations that need to be applied to that cache
  1364. to maintain coherency with the rest of the system;
  1365. (*) the coherency queue is not flushed by normal loads to lines already
  1366. present in the cache, even though the contents of the queue may
  1367. potentially effect those loads.
  1368. Imagine, then, that two writes are made on the first CPU, with a write barrier
  1369. between them to guarantee that they will appear to reach that CPU's caches in
  1370. the requisite order:
  1371. CPU 1 CPU 2 COMMENT
  1372. =============== =============== =======================================
  1373. u == 0, v == 1 and p == &u, q == &u
  1374. v = 2;
  1375. smp_wmb(); Make sure change to v visible before
  1376. change to p
  1377. <A:modify v=2> v is now in cache A exclusively
  1378. p = &v;
  1379. <B:modify p=&v> p is now in cache B exclusively
  1380. The write memory barrier forces the other CPUs in the system to perceive that
  1381. the local CPU's caches have apparently been updated in the correct order. But
  1382. now imagine that the second CPU that wants to read those values:
  1383. CPU 1 CPU 2 COMMENT
  1384. =============== =============== =======================================
  1385. ...
  1386. q = p;
  1387. x = *q;
  1388. The above pair of reads may then fail to happen in expected order, as the
  1389. cacheline holding p may get updated in one of the second CPU's caches whilst
  1390. the update to the cacheline holding v is delayed in the other of the second
  1391. CPU's caches by some other cache event:
  1392. CPU 1 CPU 2 COMMENT
  1393. =============== =============== =======================================
  1394. u == 0, v == 1 and p == &u, q == &u
  1395. v = 2;
  1396. smp_wmb();
  1397. <A:modify v=2> <C:busy>
  1398. <C:queue v=2>
  1399. p = &v; q = p;
  1400. <D:request p>
  1401. <B:modify p=&v> <D:commit p=&v>
  1402. <D:read p>
  1403. x = *q;
  1404. <C:read *q> Reads from v before v updated in cache
  1405. <C:unbusy>
  1406. <C:commit v=2>
  1407. Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
  1408. no guarantee that, without intervention, the order of update will be the same
  1409. as that committed on CPU 1.
  1410. To intervene, we need to interpolate a data dependency barrier or a read
  1411. barrier between the loads. This will force the cache to commit its coherency
  1412. queue before processing any further requests:
  1413. CPU 1 CPU 2 COMMENT
  1414. =============== =============== =======================================
  1415. u == 0, v == 1 and p == &u, q == &u
  1416. v = 2;
  1417. smp_wmb();
  1418. <A:modify v=2> <C:busy>
  1419. <C:queue v=2>
  1420. p = &v; q = p;
  1421. <D:request p>
  1422. <B:modify p=&v> <D:commit p=&v>
  1423. <D:read p>
  1424. smp_read_barrier_depends()
  1425. <C:unbusy>
  1426. <C:commit v=2>
  1427. x = *q;
  1428. <C:read *q> Reads from v after v updated in cache
  1429. This sort of problem can be encountered on DEC Alpha processors as they have a
  1430. split cache that improves performance by making better use of the data bus.
  1431. Whilst most CPUs do imply a data dependency barrier on the read when a memory
  1432. access depends on a read, not all do, so it may not be relied on.
  1433. Other CPUs may also have split caches, but must coordinate between the various
  1434. cachelets for normal memory accesses. The semantics of the Alpha removes the
  1435. need for coordination in absence of memory barriers.
  1436. CACHE COHERENCY VS DMA
  1437. ----------------------
  1438. Not all systems maintain cache coherency with respect to devices doing DMA. In
  1439. such cases, a device attempting DMA may obtain stale data from RAM because
  1440. dirty cache lines may be resident in the caches of various CPUs, and may not
  1441. have been written back to RAM yet. To deal with this, the appropriate part of
  1442. the kernel must flush the overlapping bits of cache on each CPU (and maybe
  1443. invalidate them as well).
  1444. In addition, the data DMA'd to RAM by a device may be overwritten by dirty
  1445. cache lines being written back to RAM from a CPU's cache after the device has
  1446. installed its own data, or cache lines simply present in a CPUs cache may
  1447. simply obscure the fact that RAM has been updated, until at such time as the
  1448. cacheline is discarded from the CPU's cache and reloaded. To deal with this,
  1449. the appropriate part of the kernel must invalidate the overlapping bits of the
  1450. cache on each CPU.
  1451. See Documentation/cachetlb.txt for more information on cache management.
  1452. CACHE COHERENCY VS MMIO
  1453. -----------------------
  1454. Memory mapped I/O usually takes place through memory locations that are part of
  1455. a window in the CPU's memory space that have different properties assigned than
  1456. the usual RAM directed window.
  1457. Amongst these properties is usually the fact that such accesses bypass the
  1458. caching entirely and go directly to the device buses. This means MMIO accesses
  1459. may, in effect, overtake accesses to cached memory that were emitted earlier.
  1460. A memory barrier isn't sufficient in such a case, but rather the cache must be
  1461. flushed between the cached memory write and the MMIO access if the two are in
  1462. any way dependent.
  1463. =========================
  1464. THE THINGS CPUS GET UP TO
  1465. =========================
  1466. A programmer might take it for granted that the CPU will perform memory
  1467. operations in exactly the order specified, so that if a CPU is, for example,
  1468. given the following piece of code to execute:
  1469. a = *A;
  1470. *B = b;
  1471. c = *C;
  1472. d = *D;
  1473. *E = e;
  1474. They would then expect that the CPU will complete the memory operation for each
  1475. instruction before moving on to the next one, leading to a definite sequence of
  1476. operations as seen by external observers in the system:
  1477. LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
  1478. Reality is, of course, much messier. With many CPUs and compilers, the above
  1479. assumption doesn't hold because:
  1480. (*) loads are more likely to need to be completed immediately to permit
  1481. execution progress, whereas stores can often be deferred without a
  1482. problem;
  1483. (*) loads may be done speculatively, and the result discarded should it prove
  1484. to have been unnecessary;
  1485. (*) loads may be done speculatively, leading to the result having being
  1486. fetched at the wrong time in the expected sequence of events;
  1487. (*) the order of the memory accesses may be rearranged to promote better use
  1488. of the CPU buses and caches;
  1489. (*) loads and stores may be combined to improve performance when talking to
  1490. memory or I/O hardware that can do batched accesses of adjacent locations,
  1491. thus cutting down on transaction setup costs (memory and PCI devices may
  1492. both be able to do this); and
  1493. (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
  1494. mechanisms may alleviate this - once the store has actually hit the cache
  1495. - there's no guarantee that the coherency management will be propagated in
  1496. order to other CPUs.
  1497. So what another CPU, say, might actually observe from the above piece of code
  1498. is:
  1499. LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
  1500. (Where "LOAD {*C,*D}" is a combined load)
  1501. However, it is guaranteed that a CPU will be self-consistent: it will see its
  1502. _own_ accesses appear to be correctly ordered, without the need for a memory
  1503. barrier. For instance with the following code:
  1504. U = *A;
  1505. *A = V;
  1506. *A = W;
  1507. X = *A;
  1508. *A = Y;
  1509. Z = *A;
  1510. and assuming no intervention by an external influence, it can be assumed that
  1511. the final result will appear to be:
  1512. U == the original value of *A
  1513. X == W
  1514. Z == Y
  1515. *A == Y
  1516. The code above may cause the CPU to generate the full sequence of memory
  1517. accesses:
  1518. U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
  1519. in that order, but, without intervention, the sequence may have almost any
  1520. combination of elements combined or discarded, provided the program's view of
  1521. the world remains consistent.
  1522. The compiler may also combine, discard or defer elements of the sequence before
  1523. the CPU even sees them.
  1524. For instance:
  1525. *A = V;
  1526. *A = W;
  1527. may be reduced to:
  1528. *A = W;
  1529. since, without a write barrier, it can be assumed that the effect of the
  1530. storage of V to *A is lost. Similarly:
  1531. *A = Y;
  1532. Z = *A;
  1533. may, without a memory barrier, be reduced to:
  1534. *A = Y;
  1535. Z = Y;
  1536. and the LOAD operation never appear outside of the CPU.
  1537. AND THEN THERE'S THE ALPHA
  1538. --------------------------
  1539. The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
  1540. some versions of the Alpha CPU have a split data cache, permitting them to have
  1541. two semantically related cache lines updating at separate times. This is where
  1542. the data dependency barrier really becomes necessary as this synchronises both
  1543. caches with the memory coherence system, thus making it seem like pointer
  1544. changes vs new data occur in the right order.
  1545. The Alpha defines the Linux's kernel's memory barrier model.
  1546. See the subsection on "Cache Coherency" above.
  1547. ==========
  1548. REFERENCES
  1549. ==========
  1550. Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
  1551. Digital Press)
  1552. Chapter 5.2: Physical Address Space Characteristics
  1553. Chapter 5.4: Caches and Write Buffers
  1554. Chapter 5.5: Data Sharing
  1555. Chapter 5.6: Read/Write Ordering
  1556. AMD64 Architecture Programmer's Manual Volume 2: System Programming
  1557. Chapter 7.1: Memory-Access Ordering
  1558. Chapter 7.4: Buffering and Combining Memory Writes
  1559. IA-32 Intel Architecture Software Developer's Manual, Volume 3:
  1560. System Programming Guide
  1561. Chapter 7.1: Locked Atomic Operations
  1562. Chapter 7.2: Memory Ordering
  1563. Chapter 7.4: Serializing Instructions
  1564. The SPARC Architecture Manual, Version 9
  1565. Chapter 8: Memory Models
  1566. Appendix D: Formal Specification of the Memory Models
  1567. Appendix J: Programming with the Memory Models
  1568. UltraSPARC Programmer Reference Manual
  1569. Chapter 5: Memory Accesses and Cacheability
  1570. Chapter 15: Sparc-V9 Memory Models
  1571. UltraSPARC III Cu User's Manual
  1572. Chapter 9: Memory Models
  1573. UltraSPARC IIIi Processor User's Manual
  1574. Chapter 8: Memory Models
  1575. UltraSPARC Architecture 2005
  1576. Chapter 9: Memory
  1577. Appendix D: Formal Specifications of the Memory Models
  1578. UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
  1579. Chapter 8: Memory Models
  1580. Appendix F: Caches and Cache Coherency
  1581. Solaris Internals, Core Kernel Architecture, p63-68:
  1582. Chapter 3.3: Hardware Considerations for Locks and
  1583. Synchronization
  1584. Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
  1585. for Kernel Programmers:
  1586. Chapter 13: Other Memory Models
  1587. Intel Itanium Architecture Software Developer's Manual: Volume 1:
  1588. Section 2.6: Speculation
  1589. Section 4.4: Memory Access